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m1n1 : add initial support for T6030 #426

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The system counter frequency (CNTFRQ_EL0) varies between the efficiency and performance cores on the M3. The efficiency cores run at 1 GHz, as required by Armv8.6-A, while the performance cores continue to utilize Apple's standard frequency of 24 MHz. Hypervisor still does not work yet due to missing counter scaling bit in order to switch in EL1.

With that said Linux boots on the M3 Pro using all 11 cores(performance and efficiency) with a very limited configuration:
interrupt controller and uart for now able to reach penguins.
Linux DT : https://github.com/a-ramses/linux/tree/t6030-j514s.
This patch relies on changes to parse "spmi-cha**" @jannau

a-ramses and others added 6 commits December 13, 2024 01:18
apsc cannot be initialized using bit 40 on the PCPU cluster without triggering an SError but can be set on ECPU

Signed-off-by: a-ramses <[email protected]>
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jannau commented Dec 14, 2024

Please ensure thta each commit is properly formatted, i.e. fold the changes from commit 5e7a5cf into the commits which caused the format errors. That would also solve the missing signoff in that commit

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