Merge remote-tracking branch 'origin/master' into fpc

BerkeleyHCI · Sep 21, 2024 · 05bd6fb · 05bd6fb
2 parents d3f4e27 + 353e803
commit 05bd6fb
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Showing 3 changed files with 10 additions and 7 deletions.
diff --git a/edg/parts/Camera_Ov2640_Fpc24.py b/edg/parts/Camera_Ov2640_Fpc24.py
@@ -2,7 +2,7 @@
 from .PassiveConnector_Fpc import Fpc050Bottom
 
 
-class Ov2640_Fpc24_Device(InternalSubcircuit, Block):
+class Ov2640_Fpc24_Device(InternalSubcircuit, Nonstrict3v3Compatible, Block):
     def __init__(self) -> None:
         super().__init__()
 
@@ -11,11 +11,13 @@ def __init__(self) -> None:
         self.dgnd = self.Export(self.conn.pins.request('10').adapt_to(Ground()))
         self.agnd = self.Export(self.conn.pins.request('23').adapt_to(Ground()))
         self.dovdd = self.Export(self.conn.pins.request('14').adapt_to(VoltageSink(
-            voltage_limits=(1.71, 3.3)*Volt,  # Table 6, absolute maximum (Table 5) is 4.5v
+            voltage_limits=self.nonstrict_3v3_compatible.then_else(
+                (1.71, 4.5)*Volt,  # Table 6, absolute maximum (Table 5) is 4.5v
+                (1.71, 3.3)*Volt),
             current_draw=(6, 15)*mAmp  # active typ to max
         )))
         self.dvdd = self.Export(self.conn.pins.request('15').adapt_to(VoltageSink(
-            voltage_limits=(1.24, 1.36)*Volt,  # Table 6
+            voltage_limits=(1.14, 1.26)*Volt,  # Table 6
             current_draw=(30, 60)*mAmp  # active typ YUV to max compressed
         )))
         self.avdd = self.Export(self.conn.pins.request('21').adapt_to(VoltageSink(

diff --git a/edg/parts/JlcResistor.py b/edg/parts/JlcResistor.py
@@ -51,8 +51,11 @@ def parse_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]:
         new_cols[cls.POWER_RATING] = Range.zero_to_upper(
           PartParserUtil.parse_value(extracted_values['power'][1], 'W'))
 
-        new_cols[cls.VOLTAGE_RATING] = Range.zero_to_upper(
-          PartParserUtil.parse_value(extracted_values['voltage'][1], 'V'))
+        if 'voltage' in extracted_values:
+          new_cols[cls.VOLTAGE_RATING] = Range.zero_to_upper(
+          PartParserUtil.parse_value(extracted_values.get('voltage', ('', '0V'))[1], 'V'))
+        else:
+          new_cols[cls.VOLTAGE_RATING] = Range(0, 0)
 
         return new_cols
       except (KeyError, PartParserUtil.ParseError):

diff --git a/examples/test_pcbbot.py b/examples/test_pcbbot.py
@@ -220,8 +220,6 @@ def refinements(self) -> Refinements:
         (CompactKeystone5015, ['lcsc_part'], 'C5199798'),  # RH-5015, which is actually in stock
 
         # the camera recommended specs are excessively tight, so loosen them a bit
-        (Ov2640_Fpc24, ['device', 'dovdd', 'voltage_limits'], Range(1.71, 4.5)),
-        (Ov2640_Fpc24, ['device', 'dvdd', 'voltage_limits'], Range(1.1, 1.36)),  # allow 1v2
         (Ov2640_Fpc24, ['device', 'avdd', 'voltage_limits'], Range(2.3, 3.0)),  # allow 2v5
         (Nonstrict3v3Compatible, ['nonstrict_3v3_compatible'], True),
       ],