Add analog signal range modeling

[ducky64]

voltage_out now means the voltage the device is capable of generating (even as an unintended transient), while signal_out is the voltage the device generates under normal operating conditions. voltage_limit now refers the maximum operating condition (sometimes the absolute maximum rating), while signal_limit is the functional operating limit (which may differ from the maximum rating, e.g. for a non-RRIO opamp or weirder ADCs - looking at you ESP32). Basically adds automated checking for those edge cases.

Updates all part models with signal modelling.

Other changes:

• Enforce voltage_limits for AnalogLinks - apparently the assertion was missing before...
• Updates the compiler to handle RangeEmpty in additions and multiplications.
• Add AnalogClampZenerDiode, to clamp analog voltage
• Clean up some of the analog port definitions
• Add ResistiveDivider.divider_output and divider_ratio utility to share these common calculation functions

Future things to do:

• Generate the proper signal output range for opamp amplifiers and diffamps - currently it's intersected with the amp output range to avoid excessive large ranges as a result of input tolerances.