Continued example boards

edg/BoardTop.py

@@ -24,7 +24,7 @@ def refinements(self) -> Refinements:
         (Fet, JlcFet),  # TODO: replace with non-distributor parts list
         (SwitchFet, JlcSwitchFet),  # TODO: replace with non-distributor parts list
         (Led, SmtLed),
-        (RgbLedCommonAnode, SmtRgbLed),
+        (RgbLedCommonAnode, Smt0606RgbLed),
         (Crystal, JlcCrystal),  # TODO: replace with non-distributor parts list
         (Oscillator, JlcOscillator),  # TODO: replace with non-distributor parts list
 
@@ -79,6 +79,7 @@ def refinements(self) -> Refinements:
         (Diode, JlcDiode),
         (Bjt, JlcBjt),
         (Fet, JlcFet),
+        (Antenna, JlcAntenna),
 
         (Fpc050Bottom, Afc01),
         (Fpc050Top, Afc07Top),

edg_core/ArrayExpr.py

@@ -86,6 +86,9 @@ def _create_unary_set_op(self, op: Union[NumericOp, BoolOp, RangeSetOp, EqOp]) -
   def all_unique(self) -> BoolExpr:
     return BoolExpr()._new_bind(UnarySetOpBinding(self, EqOp.all_unique))
 
+  def all_equal(self) -> BoolExpr:
+    return BoolExpr()._new_bind(UnarySetOpBinding(self, EqOp.all_equal))
+
   def sum(self) -> ArrayEltType:
     return self._create_unary_set_op(NumericOp.sum)
 

edg_core/HierarchyBlock.py

@@ -403,7 +403,7 @@ def chain(self, *elts: Union[Connection, BasePort, Block]) -> ChainConnect:
       current_port = outable_ports[0]
       chain_blocks.append(elts[0])
     else:
-      raise EdgTypeError(f"first element 0 to chain", elts[0], (BasePort, Block))
+      raise EdgTypeError(f"first element 0 to chain", elts[0], (BasePort, Connection, Block))
 
     for i, elt in list(enumerate(elts))[1:-1]:
       elt = assert_cast(elt, (Block), f"middle arguments elts[{i}] to chain")
@@ -426,7 +426,7 @@ def chain(self, *elts: Union[Connection, BasePort, Block]) -> ChainConnect:
       else:
         raise ChainError(self, f"element {i} to chain {type(elt)} has no Input and Output, or InOut ports")
 
-    if isinstance(elts[-1], BasePort):
+    if isinstance(elts[-1], (BasePort, Connection)):
       chain_links.append(self.connect(current_port, elts[-1]))
     elif isinstance(elts[-1], Block):
       inable_ports = elts[-1]._get_ports_by_tag({Input}) + elts[-1]._get_ports_by_tag({InOut})
@@ -435,7 +435,7 @@ def chain(self, *elts: Union[Connection, BasePort, Block]) -> ChainConnect:
       chain_blocks.append(elts[-1])
       chain_links.append(self.connect(current_port, inable_ports[0]))
     else:
-      raise EdgTypeError(f"last argument {len(elts) - 1} to chain", elts[-1], (BasePort, Block))
+      raise EdgTypeError(f"last argument {len(elts) - 1} to chain", elts[-1], (BasePort, Connection, Block))
 
     return self._chains.register(ChainConnect(chain_blocks, chain_links))
 

electronics_abstract_parts/AbstractAntenna.py

@@ -0,0 +1,48 @@
+from electronics_model import *
+from .Categories import *
+from .PartsTable import PartsTableColumn, PartsTableRow
+from .PartsTablePart import PartsTableSelector
+
+
+@abstract_block
+class Antenna(Block):
+  @init_in_parent
+  def __init__(self, frequency: RangeLike, impedance: RangeLike = Range.all(), power: RangeLike = (0, 0*Watt)):
+    super().__init__()
+
+    self.frequency = self.ArgParameter(frequency)
+    self.actual_frequency_rating = self.Parameter(RangeExpr())
+
+    self.impedance = self.ArgParameter(impedance)
+    self.actual_impedance = self.Parameter(RangeExpr())
+
+    self.power = self.ArgParameter(power)
+    self.actual_power_rating = self.Parameter(RangeExpr())
+
+    self.a = self.Port(Passive.empty())
+
+
+@non_library
+class TableAntenna(Antenna, PartsTableSelector, GeneratorBlock):
+  REFDES_PREFIX = 'ANT'
+
+  FREQUENCY_RATING = PartsTableColumn(Range)
+  IMPEDANCE = PartsTableColumn(Range)
+  POWER_RATING = PartsTableColumn(Range)
+
+  @init_in_parent
+  def __init__(self, *args, **kwargs):
+    super().__init__(*args, **kwargs)
+    self.generator_param(self.frequency, self.power, self.impedance)
+
+  def _row_filter(self, row: PartsTableRow) -> bool:
+    return super()._row_filter(row) and \
+      self.get(self.frequency).fuzzy_in(row[self.FREQUENCY_RATING]) and \
+      row[self.IMPEDANCE].fuzzy_in(self.get(self.impedance)) and\
+      self.get(self.power).fuzzy_in(row[self.POWER_RATING])
+
+  def _row_generate(self, row: PartsTableRow) -> None:
+    super()._row_generate(row)
+    self.assign(self.actual_frequency_rating, row[self.FREQUENCY_RATING])
+    self.assign(self.actual_power_rating, row[self.POWER_RATING])
+    self.assign(self.actual_impedance, row[self.IMPEDANCE])

electronics_abstract_parts/AbstractCapacitor.py

@@ -64,10 +64,13 @@ def parse_capacitor(cls, value: str) -> Tuple[Range, Range]:
     center = PartParserUtil.parse_value(match.group(1), '')
     voltage = PartParserUtil.parse_value(match.group(3), 'V')
     if match.group(2) is not None:
-      tolerance = PartParserUtil.parse_tolerance(match.group(2))
+      tol_str = match.group(2)
+      if not tol_str.startswith('±'):  # format conversion to more strict parser
+        tol_str = '±' + tol_str
+      capacitance = PartParserUtil.parse_abs_tolerance(tol_str, center, 'F')
     else:
-      tolerance = (-cls.CAPACITOR_DEFAULT_TOL, cls.CAPACITOR_DEFAULT_TOL)
-    return (Range.from_tolerance(center, tolerance), Range.zero_to_upper(voltage))
+      capacitance = Range.from_tolerance(center, (-cls.CAPACITOR_DEFAULT_TOL, cls.CAPACITOR_DEFAULT_TOL))
+    return (capacitance, Range.zero_to_upper(voltage))
 
   @classmethod
   def block_from_symbol(cls, symbol_name: str, properties: Mapping[str, str]) -> 'Capacitor':
@@ -171,6 +174,8 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]
           factor = self.DERATE_LOWEST
         derated = row[self.CAPACITANCE] * Range(factor, 1)
 
+      if derated.lower == 0:  # in case where tolerance is the nominal value
+        return None
       count = math.ceil(self.get(self.capacitance).lower / derated.lower)
       derated_parallel_capacitance = derated * count
       if not derated_parallel_capacitance.fuzzy_in(self.get(self.capacitance)):  # not satisfying spec, remove row
@@ -182,7 +187,7 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]
               self.PARALLEL_CAPACITANCE: row[self.CAPACITANCE] * count}
 
     return table.map_new_columns(add_derated_row).filter(lambda row: (
-        row[self.PARALLEL_DERATED_CAPACITANCE] in self.get(self.capacitance)
+            row[self.PARALLEL_DERATED_CAPACITANCE] in self.get(self.capacitance)
     ))
 
   def _row_generate(self, row: PartsTableRow) -> None:
@@ -257,3 +262,52 @@ def connected(self, gnd: Optional[Port[VoltageLink]] = None, pwr: Optional[Port[
     if pwr is not None:
       cast(Block, builder.get_enclosing_block()).connect(pwr, self.pwr)
     return self
+
+
+class CombinedCapacitorElement(Capacitor):  # to avoid an abstract part error
+  def contents(self):
+    super().contents()
+    self.assign(self.actual_capacitance, self.capacitance)  # fake it, since a combined capacitance is handwavey
+
+
+class CombinedCapacitor(PassiveComponent, MultipackBlock, GeneratorBlock):
+  """A packed capacitor that combines multiple individual capacitors into a single component,
+  with the sum of or taking the max of the constituent capacitances."""
+  @init_in_parent
+  def __init__(self, *, extend_upper: BoolLike = False) -> None:
+    super().__init__()
+
+    self.elements = self.PackedPart(PackedBlockArray(CombinedCapacitorElement()))
+    self.pos = self.PackedExport(self.elements.ports_array(lambda x: x.pos))
+    self.neg = self.PackedExport(self.elements.ports_array(lambda x: x.neg))
+    self.capacitances = self.PackedParameter(self.elements.params_array(lambda x: x.capacitance))
+    self.voltages = self.PackedParameter(self.elements.params_array(lambda x: x.voltage))
+    self.voltage_rating_deratings = self.PackedParameter(self.elements.params_array(lambda x: x.voltage_rating_derating))
+    self.exact_capacitances = self.PackedParameter(self.elements.params_array(lambda x: x.exact_capacitance))
+
+    self.actual_capacitance = self.Parameter(RangeExpr())
+    self.actual_voltage_rating = self.Parameter(RangeExpr())
+    self.unpacked_assign(self.elements.params(lambda x: x.actual_voltage_rating), self.actual_voltage_rating)
+
+    self.extend_upper = self.ArgParameter(extend_upper)
+    self.generator_param(self.pos.requested(), self.neg.requested(), self.extend_upper)
+
+
+  def generate(self):
+    super().generate()
+    capacitance = self.capacitances.sum()
+    if self.get(self.extend_upper):
+      capacitance = RangeExpr._to_expr_type((capacitance.lower(), float('inf')))
+    self.cap = self.Block(Capacitor(capacitance, voltage=self.voltages.hull(),
+                                    exact_capacitance=self.exact_capacitances.all(),
+                                    voltage_rating_derating=self.voltage_rating_deratings.min()))
+    self.assign(self.actual_voltage_rating, self.cap.actual_voltage_rating)
+    self.assign(self.actual_capacitance, self.cap.actual_capacitance)
+    self.require(self.exact_capacitances.all_equal())
+
+    self.pos_merge = self.Block(PackedPassive())
+    self.neg_merge = self.Block(PackedPassive())
+    self.connect(self.cap.pos, self.pos_merge.merged)
+    self.connect(self.cap.neg, self.neg_merge.merged)
+    self.connect(self.pos, self.pos_merge.elts)
+    self.connect(self.neg, self.neg_merge.elts)

electronics_abstract_parts/AbstractCrystal.py

@@ -45,6 +45,12 @@ class CrystalStandardFootprint(Crystal, StandardFootprint[Crystal]):
       '3': block.crystal.xtal_out,
       '4': block.gnd,
     },
+    'Crystal:Crystal_SMD_2520-4Pin_2.5x2.0mm': lambda block: {
+      '1': block.crystal.xtal_in,
+      '2': block.gnd,
+      '3': block.crystal.xtal_out,
+      '4': block.gnd,
+    },
   }
 
 

electronics_abstract_parts/AbstractDebugHeaders.py

@@ -17,7 +17,7 @@ class SwdCortexTargetConnectorReset(BlockInterfaceMixin[SwdCortexTargetConnector
   """Mixin for SWD connectors with adding the optional reset pin"""
   def __init__(self, *args, **kwargs) -> None:
     super().__init__(*args, **kwargs)
-    self.reset = self.Port(DigitalBidir.empty())  # can tri-state when not asserted
+    self.reset = self.Port(DigitalBidir.empty(), optional=True)  # can tri-state when not asserted
 
 
 class SwdCortexTargetConnectorSwo(BlockInterfaceMixin[SwdCortexTargetConnector]):

electronics_abstract_parts/AbstractDiodes.py

@@ -175,7 +175,6 @@ def contents(self):
     self.diode = self.Block(ZenerDiode(zener_voltage=self.voltage))
     self.connect(self.diode.cathode.adapt_to(VoltageSink(
       voltage_limits=(0, self.diode.actual_zener_voltage.lower()),
-      current_draw=(0, 0)*Amp  # TODO should be leakage current
     )), self.pwr)
     self.connect(self.diode.anode.adapt_to(Ground()), self.gnd)
 

electronics_abstract_parts/AbstractInductor.py

@@ -1,4 +1,4 @@
-from typing import Dict
+from typing import Dict, Optional, cast
 
 from electronics_model import *
 from .PartsTable import PartsTableColumn, PartsTableRow
@@ -151,3 +151,34 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_inductance, row[self.INDUCTANCE])
     self.assign(self.actual_current_rating, row[self.CURRENT_RATING])
     self.assign(self.actual_frequency_rating, row[self.FREQUENCY_RATING])
+
+
+class SeriesPowerInductor(DiscreteApplication):
+  """VoltageSource/Sink-typed series inductor for power filtering"""
+  @init_in_parent
+  def __init__(self, inductance: RangeLike, current: RangeLike = RangeExpr.ZERO,
+               frequency: RangeLike = RangeExpr.ZERO) -> None:
+    super().__init__()
+
+    self.pwr_out = self.Port(VoltageSource.empty(), [Output])  # forward declaration
+    self.pwr_in = self.Port(VoltageSink.empty(), [Power, Input])  # forward declaration
+
+    self.ind = self.Block(Inductor(
+      inductance=inductance, current=current, frequency=frequency
+    ))
+
+    self.connect(self.pwr_in, self.ind.a.adapt_to(VoltageSink(
+      current_draw=self.pwr_out.link().current_drawn
+    )))
+    self.connect(self.pwr_out, self.ind.b.adapt_to(VoltageSource(
+      voltage_out=self.pwr_in.link().voltage,
+    )))
+
+  def connected(self, pwr_in: Optional[Port[VoltageLink]] = None, pwr_out: Optional[Port[VoltageLink]] = None) -> \
+      'SeriesPowerInductor':
+    """Convenience function to connect both ports, returning this object so it can still be given a name."""
+    if pwr_in is not None:
+      cast(Block, builder.get_enclosing_block()).connect(pwr_in, self.pwr_in)
+    if pwr_out is not None:
+      cast(Block, builder.get_enclosing_block()).connect(pwr_out, self.pwr_out)
+    return self

electronics_abstract_parts/AbstractLed.py

@@ -15,6 +15,7 @@ class Led(DiscreteSemiconductor):
   Blue: LedColor = "blue"
   Yellow: LedColor = "yellow"
   White: LedColor = "white"
+  Orange: LedColor = "orange"
   Any: LedColor = ""
 
   @init_in_parent

electronics_abstract_parts/AbstractOpamp.py

@@ -25,3 +25,7 @@ def __init__(self) -> None:
     self.inp = self.Port(AnalogSink.empty())
     self.inn = self.Port(AnalogSink.empty())
     self.out = self.Port(AnalogSource.empty())
+
+
+class OpampElement(Opamp):
+  """Packed opamp element"""

electronics_abstract_parts/AbstractPowerConverters.py

@@ -151,7 +151,7 @@ def __init__(self, *args, ripple_current_factor: RangeLike,
     self.input_ripple_limit = self.ArgParameter(input_ripple_limit)
     self.output_ripple_limit = self.ArgParameter(output_ripple_limit)
 
-    self.frequency = self.Parameter(RangeExpr())
+    self.actual_frequency = self.Parameter(RangeExpr())
 
 
 @abstract_block_default(lambda: IdealBuckConverter)
@@ -199,9 +199,9 @@ class BuckConverterPowerPath(InternalSubcircuit, GeneratorBlock):
   @init_in_parent
   def __init__(self, input_voltage: RangeLike, output_voltage: RangeLike, frequency: RangeLike,
                output_current: RangeLike, current_limits: RangeLike, inductor_current_ripple: RangeLike, *,
+               input_voltage_ripple: FloatLike,
+               output_voltage_ripple: FloatLike,
                efficiency: RangeLike = (0.9, 1.0),  # from TI reference
-               input_voltage_ripple: FloatLike = 75*mVolt,
-               output_voltage_ripple: FloatLike = 25*mVolt,
                dutycycle_limit: RangeLike = (0.1, 0.9),
                inductor_scale: FloatLike = 1.0):  # arbitrary
     super().__init__()

electronics_abstract_parts/AbstractResistor.py

@@ -19,15 +19,17 @@ def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]:
     return {'1': self.a, '2': self.b}
 
   @classmethod
-  def parse_resistor(cls, value: str):
+  def parse_resistor(cls, value: str) -> Range:
     match = cls.RESISTOR_REGEX.match(value)
     assert match is not None, f"could not parse resistor from value '{value}'"
     center = PartParserUtil.parse_value(match.group(1), '')
     if match.group(2) is not None:
-      tolerance = PartParserUtil.parse_tolerance(match.group(2))
+      tol_str = match.group(2)
+      if not tol_str.startswith('±'):  # format conversion to more strict parser
+        tol_str = '±' + tol_str
+      return PartParserUtil.parse_abs_tolerance(tol_str, center, 'Ω')
     else:
-      tolerance = (-cls.RESISTOR_DEFAULT_TOL, cls.RESISTOR_DEFAULT_TOL)
-    return Range.from_tolerance(center, tolerance)
+      return Range.from_tolerance(center, (-cls.RESISTOR_DEFAULT_TOL, cls.RESISTOR_DEFAULT_TOL))
 
   @classmethod
   def block_from_symbol(cls, symbol_name: str, properties: Mapping[str, str]) -> 'Resistor':
@@ -234,12 +236,10 @@ def __init__(self, resistance: RangeLike) -> None:
     ))
 
     self.connect(self.pwr_in, self.res.a.adapt_to(VoltageSink(
-      voltage_limits=(-float('inf'), float('inf')),
       current_draw=self.pwr_out.link().current_drawn
     )))
     self.connect(self.pwr_out, self.res.b.adapt_to(VoltageSource(
       voltage_out=self.pwr_in.link().voltage,  # ignore voltage drop
-      current_limits=Range.all()
     )))
 
     self.actual_power = self.Parameter(RangeExpr(current_draw * current_draw * self.res.actual_resistance))