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JIT bugfixes
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- bugfix shift opcodes
- bugfix CMP.W (32 bit only)
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@midwan
midwan committed Feb 18, 2020
1 parent 959f086 commit 077dab0
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Showing 5 changed files with 63 additions and 16 deletions.
4 changes: 2 additions & 2 deletions src/jit/codegen_arm.cpp.in
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Original file line number Diff line number Diff line change
Expand Up @@ -223,9 +223,9 @@ LOWFUNC(WRITE,RMW,2,compemu_raw_inc_opcount,(IM16 op))
uae_s32 offs = data_long_offs(op);
LDR_rRI(REG_WORK3, RPC_INDEX, offs);
#endif
LDR_rRr_LSLi(REG_WORK1, REG_WORK2, REG_WORK3, 2);
LDR_rRR_LSLi(REG_WORK1, REG_WORK2, REG_WORK3, 2);
ADD_rri(REG_WORK1, REG_WORK1, 1);
STR_rRr_LSLi(REG_WORK1, REG_WORK2, REG_WORK3, 2);
STR_rRR_LSLi(REG_WORK1, REG_WORK2, REG_WORK3, 2);
}
LENDFUNC(WRITE,RMW,1,compemu_raw_inc_opcount,(IM16 op))

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4 changes: 3 additions & 1 deletion src/jit/compemu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -188,7 +188,7 @@ STATIC_INLINE int end_block(uae_u16 opcode)
#define PC_P 16
#define FLAGX 17
#define FLAGTMP 18
// Is S4 ever in use?

#define S1 19
#define S2 20
#define S3 21
Expand All @@ -200,9 +200,11 @@ STATIC_INLINE int end_block(uae_u16 opcode)
#define SCRATCH_F64_1 1
#define SCRATCH_F64_2 2
#define SCRATCH_F64_3 3
#define SCRATCH_F64_4 4
#define SCRATCH_F32_1 2
#define SCRATCH_F32_2 4
#define SCRATCH_F32_3 6
#define SCRATCH_F32_4 8

typedef struct {
uae_u32 touched;
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26 changes: 24 additions & 2 deletions src/jit/compemu_midfunc_arm2.cpp.in
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Original file line number Diff line number Diff line change
Expand Up @@ -1161,6 +1161,8 @@ MIDFUNC(2,jnf_ASR_b_imm,(RW1 d, IM8 i))
d = rmw(d);

SIGNED8_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
ASR_rri(REG_WORK1, REG_WORK1, i);
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK1, 0, 7);
Expand All @@ -1181,6 +1183,8 @@ MIDFUNC(2,jnf_ASR_w_imm,(RW2 d, IM8 i))
d = rmw(d);

SIGNED16_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
PKHTB_rrrASRi(d, d, REG_WORK1, i);

unlock2(d);
Expand All @@ -1193,6 +1197,8 @@ MIDFUNC(2,jnf_ASR_l_imm,(RW4 d, IM8 i))
if(i) {
d = rmw(d);

if(i > 31)
i = 31;
ASR_rri(d, d, i);

unlock2(d);
Expand All @@ -1210,6 +1216,8 @@ MIDFUNC(2,jff_ASR_b_imm,(RW1 d, IM8 i))
SIGNED8_REG_2_REG(REG_WORK1, d);
MSR_CPSRf_i(0);
if (i) {
if(i > 31)
i = 31;
ASRS_rri(REG_WORK1, REG_WORK1, i);
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK1, 0, 7);
Expand Down Expand Up @@ -1239,6 +1247,8 @@ MIDFUNC(2,jff_ASR_w_imm,(RW2 d, IM8 i))
SIGNED16_REG_2_REG(REG_WORK1, d);
MSR_CPSRf_i(0);
if (i) {
if(i > 31)
i = 31;
ASRS_rri(REG_WORK1, REG_WORK1, i);
PKHTB_rrr(d, d, REG_WORK1);
flags_carry_inverted = false;
Expand All @@ -1261,6 +1271,10 @@ MIDFUNC(2,jff_ASR_l_imm,(RW4 d, IM8 i))

MSR_CPSRf_i(0);
if (i) {
if (i > 31) {
ASR_rri(d, d, 1); // make sure, msb is shifted out at least once
i = 31;
}
ASRS_rri(d, d, i);
flags_carry_inverted = false;
DUPLICACTE_CARRY
Expand Down Expand Up @@ -2158,8 +2172,8 @@ MENDFUNC(2,jff_CMP_b,(RR1 d, RR1 s))
MIDFUNC(2,jff_CMP_w,(RR2 d, RR2 s))
{
if (isconst(d) && isconst(s)) {
SIGNED16_IMM_2_REG(REG_WORK1, live.state[d].val & 0xff);
SIGNED16_IMM_2_REG(REG_WORK2, live.state[s].val & 0xff);
SIGNED16_IMM_2_REG(REG_WORK1, live.state[d].val & 0xffff);
SIGNED16_IMM_2_REG(REG_WORK2, live.state[s].val & 0xffff);
CMP_rr(REG_WORK1, REG_WORK2);
} else {
INIT_RREGS_w(d, s);
Expand Down Expand Up @@ -3079,6 +3093,8 @@ MIDFUNC(2,jnf_LSL_b_imm,(RW1 d, IM8 i))

INIT_REG_b(d);

if(i > 31)
i = 31;
LSL_rri(REG_WORK1, d, i);
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK1, 0, 7);
Expand All @@ -3103,6 +3119,8 @@ MIDFUNC(2,jnf_LSL_w_imm,(RW2 d, IM8 i))

INIT_REG_w(d);

if(i > 31)
i = 31;
LSL_rri(REG_WORK1, d, i);
PKHTB_rrr(d, d, REG_WORK1);

Expand Down Expand Up @@ -3438,6 +3456,8 @@ MIDFUNC(2,jnf_LSR_b_imm,(RW1 d, IM8 i))
INIT_REG_b(d);

UNSIGNED8_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
LSR_rri(REG_WORK1, REG_WORK1, i);
#ifdef ARMV6T2
BFI_rrii(d, REG_WORK1, 0, 7);
Expand All @@ -3463,6 +3483,8 @@ MIDFUNC(2,jnf_LSR_w_imm,(RW2 d, IM8 i))
INIT_REG_w(d);

UNSIGNED16_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
PKHTB_rrrASRi(d, d, REG_WORK1, i);

unlock2(d);
Expand Down
32 changes: 32 additions & 0 deletions src/jit/compemu_midfunc_armA64_2.cpp.in
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Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,11 @@ MENDFUNC(3,jnf_ADD_im8,(W4 d, RR4 s, IM8 v))

MIDFUNC(2,jnf_ADD_b_imm,(RW1 d, IM8 v))
{
if (isconst(d)) {
live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val + v) & 0x000000ff);
return;
}

INIT_REG_b(d);

if(targetIsReg) {
Expand Down Expand Up @@ -626,6 +631,11 @@ MENDFUNC(2,jnf_AND_b,(RW1 d, RR1 s))

MIDFUNC(2,jnf_AND_w_imm,(RW2 d, IM16 v))
{
if (isconst(d)) {
live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val & v) & 0x0000ffff);
return;
}

INIT_REG_w(d);

MOVN_xi(REG_WORK1, (~v));
Expand Down Expand Up @@ -1149,6 +1159,8 @@ MIDFUNC(2,jnf_ASR_b_imm,(RW1 d, IM8 i))
d = rmw(d);

SIGNED8_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
ASR_wwi(REG_WORK1, REG_WORK1, i);
BFI_xxii(d, REG_WORK1, 0, 8);

Expand All @@ -1163,6 +1175,8 @@ MIDFUNC(2,jnf_ASR_w_imm,(RW2 d, IM8 i))
d = rmw(d);

SIGNED16_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
ASR_wwi(REG_WORK1, REG_WORK1, i);
BFI_xxii(d, REG_WORK1, 0, 16);

Expand All @@ -1176,6 +1190,8 @@ MIDFUNC(2,jnf_ASR_l_imm,(RW4 d, IM8 i))
if(i) {
d = rmw(d);

if(i > 31)
i = 31;
ASR_wwi(d, d, i);

unlock2(d);
Expand All @@ -1192,6 +1208,8 @@ MIDFUNC(2,jff_ASR_b_imm,(RW1 d, IM8 i))

SIGNED8_REG_2_REG(REG_WORK1, d);
if (i) {
if(i > 31)
i = 31;
ASR_wwi(REG_WORK2, REG_WORK1, i);
BFI_wwii(d, REG_WORK2, 0, 8);
TST_ww(REG_WORK2, REG_WORK2);
Expand Down Expand Up @@ -1222,6 +1240,8 @@ MIDFUNC(2,jff_ASR_w_imm,(RW2 d, IM8 i))

SIGNED16_REG_2_REG(REG_WORK1, d);
if (i) {
if(i > 31)
i = 31;
ASR_wwi(REG_WORK2, REG_WORK1, i);
BFI_wwii(d, REG_WORK2, 0, 16);
TST_ww(REG_WORK2, REG_WORK2);
Expand Down Expand Up @@ -1252,6 +1272,10 @@ MIDFUNC(2,jff_ASR_l_imm,(RW4 d, IM8 i))

if (i) {
MOV_ww(REG_WORK1, d);
if(i > 31) {
ASR_wwi(d, d, 1); // make sure, msb is shifted out at least once
i = 31;
}
ASR_wwi(d, d, i);
TST_ww(d, d);

Expand Down Expand Up @@ -3077,6 +3101,8 @@ MIDFUNC(2,jnf_LSL_b_imm,(RW1 d, IM8 i))

INIT_REG_b(d);

if(i > 31)
i = 31;
LSL_wwi(REG_WORK1, d, i);
BFI_wwii(d, REG_WORK1, 0, 8);

Expand All @@ -3095,6 +3121,8 @@ MIDFUNC(2,jnf_LSL_w_imm,(RW2 d, IM8 i))

INIT_REG_w(d);

if(i > 31)
i = 31;
LSL_wwi(REG_WORK1, d, i);
BFI_wwii(d, REG_WORK1, 0, 16);

Expand Down Expand Up @@ -3448,6 +3476,8 @@ MIDFUNC(2,jnf_LSR_b_imm,(RW1 d, IM8 i))
INIT_REG_b(d);

UNSIGNED8_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
LSR_wwi(REG_WORK1, REG_WORK1, i);
BFI_wwii(d, REG_WORK1, 0, 8);

Expand All @@ -3467,6 +3497,8 @@ MIDFUNC(2,jnf_LSR_w_imm,(RW2 d, IM8 i))
INIT_REG_w(d);

UNSIGNED16_REG_2_REG(REG_WORK1, d);
if(i > 31)
i = 31;
LSR_wwi(REG_WORK1, REG_WORK1, i);
BFI_wwii(d, REG_WORK1, 0, 16);

Expand Down
13 changes: 2 additions & 11 deletions src/jit/compemu_support.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,6 @@

#define jit_log(format, ...) \
write_log("JIT: " format "\n", ##__VA_ARGS__);
#define jit_log2(format, ...)

#ifdef JIT_DEBUG
#undef abort
Expand Down Expand Up @@ -326,15 +325,9 @@ STATIC_INLINE void adjust_jmpdep(dependency* d, cpuop_func* a)

STATIC_INLINE void set_dhtu(blockinfo* bi, cpuop_func* dh)
{
jit_log2("bi is %p", bi);
if (dh != bi->direct_handler_to_use) {
dependency* x = bi->deplist;
jit_log2("bi->deplist=%p", bi->deplist);
while (x) {
jit_log2("x is %p", x);
jit_log2("x->next is %p", x->next);
jit_log2("x->prev_p is %p", x->prev_p);

if (x->jmp_off) {
adjust_jmpdep(x, dh);
}
Expand Down Expand Up @@ -1205,7 +1198,7 @@ void sync_m68k_pc(void)
void compiler_exit(void)
{
if(current_compile_p != 0 && compiled_code != 0 && current_compile_p > compiled_code)
jit_log("JIT used size: %8d bytes\n", current_compile_p - compiled_code);
jit_log("used size: %8d bytes", current_compile_p - compiled_code);

#ifdef PROFILE_COMPILE_TIME
emul_end_time = clock();
Expand Down Expand Up @@ -1830,15 +1823,13 @@ STATIC_INLINE int block_check_checksum(blockinfo* bi)
isgood = called_check_checksum(bi) != 0;
}
if (isgood) {
jit_log2("reactivate %p/%p (%x %x/%x %x)", bi, bi->pc_p, c1, c2, bi->c1, bi->c2);
remove_from_list(bi);
add_to_active(bi);
raise_in_cl_list(bi);
bi->status = BI_ACTIVE;
} else {
/* This block actually changed. We need to invalidate it,
and set it up to be recompiled */
jit_log2("discard %p/%p (%x %x/%x %x)", bi, bi->pc_p, c1, c2, bi->c1, bi->c2);
invalidate_block(bi);
raise_in_cl_list(bi);
}
Expand Down Expand Up @@ -2125,7 +2116,7 @@ void build_comp(void)
void flush_icache_hard(int n)
{
if(current_compile_p != 0 && compiled_code != 0 && current_compile_p > compiled_code)
jit_log("JIT used size: %8d bytes\n", current_compile_p - compiled_code);
jit_log("used size: %8d bytes", current_compile_p - compiled_code);

blockinfo* bi, *dbi;

Expand Down

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