Add missing logic for some 48-bit libcalls

CE-Programming · Nov 19, 2024 · 5b150a8 · 5b150a8
1 parent 23b7826
commit 5b150a8
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Showing 4 changed files with 27 additions and 4 deletions.
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -103,9 +103,11 @@ HANDLE_LIBCALL(SCMP_I64, nullptr)
 HANDLE_LIBCALL(SCMP, nullptr)
 HANDLE_LIBCALL(ADD_I32, nullptr)
 HANDLE_LIBCALL(ADD_I32_I8, nullptr)
+HANDLE_LIBCALL(ADD_I48, nullptr)
 HANDLE_LIBCALL(ADD_I64, nullptr)
 HANDLE_LIBCALL(ADD_I128, nullptr)
 HANDLE_LIBCALL(SUB_I32, nullptr)
+HANDLE_LIBCALL(SUB_I48, nullptr)
 HANDLE_LIBCALL(SUB_I64, nullptr)
 HANDLE_LIBCALL(SUB_I128, nullptr)
 HANDLE_LIBCALL(MUL_I8, "__mulqi3")
@@ -203,8 +205,8 @@ HANDLE_LIBCALL(BITREV_I48, nullptr)
 HANDLE_LIBCALL(BITREV_I64, nullptr)
 HANDLE_LIBCALL(BITREV_I128, nullptr)
 HANDLE_LIBCALL(BSWAP_I32, nullptr)
-HANDLE_LIBCALL(BSWAP_I64, nullptr)
 HANDLE_LIBCALL(BSWAP_I48, nullptr)
+HANDLE_LIBCALL(BSWAP_I64, nullptr)
 HANDLE_LIBCALL(BSWAP_I128, nullptr)
 
 // Floating-point

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -485,6 +485,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
     switch (Size) {                                                            \
     case 32:                                                                   \
       return RTLIB::LibcallPrefix##32;                                         \
+    case 48:                                                                   \
+      return RTLIB::LibcallPrefix##48;                                         \
     case 64:                                                                   \
       return RTLIB::LibcallPrefix##64;                                         \
     case 128:                                                                  \

diff --git a/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp b/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp
@@ -60,6 +60,9 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
   auto LegalScalars24 = {s8, s16, s24};
   auto LegalScalars16 = {s8, s16};
   auto LegalScalars = Is24Bit ? LegalScalars24 : LegalScalars16;
+  auto LegalLargeScalars24 = {s32, s48, s64};
+  auto LegalLargeScalars16 = {s32, s64};
+  auto LegalLargeScalars = Is24Bit ? LegalLargeScalars24 : LegalLargeScalars16;
   auto LegalLibcallScalars24 = {s8, s16, s24, s32, s48, s64};
   auto LegalLibcallScalars16 = {s8, s16, s32, s64};
   auto LegalLibcallScalars =
@@ -158,7 +161,6 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
 
   getActionDefinitionsBuilder({G_ADD, G_SUB})
       .legalFor({s8})
-      .narrowScalarIf(all(pred24Bit, typeIs(0, s48)), changeTo(0, s24))
       .customFor(LegalLibcallScalars)
       .clampScalar(0, s8, sMax);
 
@@ -194,6 +196,7 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
       .minScalar(0, s16)
       .minScalarIf(pred24Bit, 0, s24)
       .minScalar(0, s32)
+      .minScalarIf(pred24Bit, 0, s48)
       .minScalar(0, s64)
       .maxScalar(0, s64);
 
@@ -273,7 +276,7 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
 
   getActionDefinitionsBuilder(G_ICMP)
       .legalForCartesianProduct({s1}, LegalTypes)
-      .customForCartesianProduct({s1}, {s32, s64})
+      .customForCartesianProduct({s1}, LegalLargeScalars)
       .clampScalar(1, s8, s64);
 
   getActionDefinitionsBuilder(G_FCMP)
@@ -310,7 +313,7 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
 
   getActionDefinitionsBuilder(G_BSWAP)
       .legalFor({s16})
-      .libcallFor({s32, s64})
+      .libcallFor(LegalLargeScalars)
       .clampScalar(0, s16, s64);
 
   getActionDefinitionsBuilder(G_BITREVERSE)
@@ -408,6 +411,9 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
     case 32:
       Libcall = RTLIB::NEG_I32;
       break;
+    case 48:
+      Libcall = RTLIB::NEG_I48;
+      break;
     case 64:
       Libcall = RTLIB::NEG_I64;
       break;
@@ -422,6 +428,9 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
   }
   if (LegalSize)
     return LegalizerHelper::Legalized;
+  if ((!F.hasOptSize() || MI.getOpcode() == G_ADD) &&
+      Size == (Subtarget.is24Bit() ? 48 : 32))
+    return Helper.narrowScalar(MI, 0, LLT::scalar(Size / 2));
   return Helper.libcall(MI, LocObserver);
 }
 
@@ -456,6 +465,7 @@ Z80LegalizerInfo::legalizeBitwise(LegalizerHelper &Helper, MachineInstr &MI,
     case 16: Libcall = RTLIB::NOT_I16; break;
     case 24: Libcall = RTLIB::NOT_I24; break;
     case 32: Libcall = RTLIB::NOT_I32; break;
+    case 48: Libcall = RTLIB::NOT_I48; break;
     case 64: Libcall = RTLIB::NOT_I64; break;
     }
     Type *Ty = IntegerType::get(Ctx, Size);
@@ -472,6 +482,7 @@ Z80LegalizerInfo::legalizeBitwise(LegalizerHelper &Helper, MachineInstr &MI,
     case 16: Libcall = RTLIB::AND_I16; break;
     case 24: Libcall = RTLIB::AND_I24; break;
     case 32: Libcall = RTLIB::AND_I32; break;
+    case 48: Libcall = RTLIB::AND_I48; break;
     case 64: Libcall = RTLIB::AND_I64; break;
     }
     Type *Ty = IntegerType::get(Ctx, Size);
@@ -620,6 +631,11 @@ Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper,
                 : IsSigned ? RTLIB::SCMP_I32
                            : RTLIB::CMP_I32;
       break;
+    case 48:
+      Libcall = ZeroRHS    ? RTLIB::CMP_I48_0
+                : IsSigned ? RTLIB::SCMP_I48
+                           : RTLIB::CMP_I48;
+      break;
     case 64:
       Libcall = ZeroRHS    ? RTLIB::CMP_I64_0
                 : IsSigned ? RTLIB::SCMP_I64
@@ -901,6 +917,7 @@ Z80LegalizerInfo::legalizeCtlz(LegalizerHelper &Helper,
   case 16: Libcall = RTLIB::CTLZ_I16; break;
   case 24: Libcall = RTLIB::CTLZ_I24; break;
   case 32: Libcall = RTLIB::CTLZ_I32; break;
+  case 48: Libcall = RTLIB::CTLZ_I48; break;
   case 64: Libcall = RTLIB::CTLZ_I64; break;
   }
   auto Result = createLibcall(MIRBuilder, Libcall,

diff --git a/llvm/lib/Target/Z80/Z80ISelLowering.cpp b/llvm/lib/Target/Z80/Z80ISelLowering.cpp
@@ -112,8 +112,10 @@ Z80TargetLowering::Z80TargetLowering(const Z80TargetMachine &TM,
   setLibcall(RTLIB::NEG_I64,          "_llneg",      CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::ADD_I32,          "_ladd",       CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::ADD_I32_I8,       "_ladd_b",     CallingConv::Z80_LibCall_AC);
+  setLibcall(RTLIB::ADD_I48,          "_i48add",     CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::ADD_I64,          "_lladd",      CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::SUB_I32,          "_lsub",       CallingConv::Z80_LibCall   );
+  setLibcall(RTLIB::SUB_I48,          "_i48sub",     CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::SUB_I64,          "_llsub",      CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::MUL_I8,           "_bmulu",      CallingConv::Z80_LibCall_BC);
   setLibcall(RTLIB::MUL_I16,          "_smulu",      CallingConv::Z80_LibCall   );