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Merge branch 'friedl-feat-hft_latency_opts' into 'devel'
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Optimalizace pro nízko-latenční režim

See merge request ndk/ndk-fpga!103
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@jakubcabal
jakubcabal committed Nov 14, 2024
2 parents 1652fe9 + e516002 commit 17c1279
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Showing 11 changed files with 257 additions and 127 deletions.
84 changes: 48 additions & 36 deletions comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,8 @@ entity TX_MAC_LITE is
-- Maximum number of Transactions waiting for space insertion
-- Ignored when IPG_GENERATE_EN==false
TRANS_FIFO_SIZE : natural := 128;
-- Low-latency mode: do not discard errornous frames
LL_MODE : boolean := false;
-- FPGA device name.
DEVICE : string := "STRATIX10";
-- Targeted version of Ethernet standart
Expand Down Expand Up @@ -616,42 +618,52 @@ begin
TX_MFB_DST_RDY => sp_mfb_dst_rdy
);
else generate
buffer_i : entity work.MFB_PD_ASFIFO
generic map(
ITEMS => DFIFO_ITEMS,
-- More time is needed to calculate CRC.
-- Lack of time is reported as error: "TX_MAC_LITE_CRC_INSERT: CRC32 out of sync!".
WR_PTR_ADD_LATENCY => 16,
REGIONS => MD_REGIONS,
REGION_SIZE => MD_REGION_SIZE,
BLOCK_SIZE => MD_BLOCK_SIZE,
ITEM_WIDTH => MD_ITEM_WIDTH,
DEVICE => DEVICE
)
port map(
RX_CLK => RX_CLK,
RX_RESET => RX_RESET,
RX_DATA => fd_mfb_data,
RX_SOF_POS => fd_mfb_sof_pos,
RX_EOF_POS => fd_mfb_eof_pos,
RX_SOF => fd_mfb_sof,
RX_EOF => fd_mfb_eof,
RX_SRC_RDY => fd_mfb_src_rdy,
RX_DST_RDY => fd_mfb_dst_rdy,
RX_DISCARD => fd_mfb_discard,
RX_FORCE_DISCARD => '0',
STATUS => open,

TX_CLK => TX_CLK,
TX_RESET => TX_RESET,
TX_DATA => sp_mfb_data,
TX_SOF_POS => sp_mfb_sof_pos,
TX_EOF_POS => sp_mfb_eof_pos,
TX_SOF => sp_mfb_sof,
TX_EOF => sp_mfb_eof,
TX_SRC_RDY => sp_mfb_src_rdy,
TX_DST_RDY => sp_mfb_dst_rdy
);
pdfifo_buff_g: if not LL_MODE generate
buffer_i : entity work.MFB_PD_ASFIFO
generic map(
ITEMS => DFIFO_ITEMS,
-- More time is needed to calculate CRC.
-- Lack of time is reported as error: "TX_MAC_LITE_CRC_INSERT: CRC32 out of sync!".
WR_PTR_ADD_LATENCY => 16,
REGIONS => MD_REGIONS,
REGION_SIZE => MD_REGION_SIZE,
BLOCK_SIZE => MD_BLOCK_SIZE,
ITEM_WIDTH => MD_ITEM_WIDTH,
DEVICE => DEVICE
)
port map(
RX_CLK => RX_CLK,
RX_RESET => RX_RESET,
RX_DATA => fd_mfb_data,
RX_SOF_POS => fd_mfb_sof_pos,
RX_EOF_POS => fd_mfb_eof_pos,
RX_SOF => fd_mfb_sof,
RX_EOF => fd_mfb_eof,
RX_SRC_RDY => fd_mfb_src_rdy,
RX_DST_RDY => fd_mfb_dst_rdy,
RX_DISCARD => fd_mfb_discard,
RX_FORCE_DISCARD => '0',
STATUS => open,

TX_CLK => TX_CLK,
TX_RESET => TX_RESET,
TX_DATA => sp_mfb_data,
TX_SOF_POS => sp_mfb_sof_pos,
TX_EOF_POS => sp_mfb_eof_pos,
TX_SOF => sp_mfb_sof,
TX_EOF => sp_mfb_eof,
TX_SRC_RDY => sp_mfb_src_rdy,
TX_DST_RDY => sp_mfb_dst_rdy
);
else generate
sp_mfb_data <= fd_mfb_data;
sp_mfb_sof_pos <= fd_mfb_sof_pos;
sp_mfb_eof_pos <= fd_mfb_eof_pos;
sp_mfb_sof <= fd_mfb_sof;
sp_mfb_eof <= fd_mfb_eof;
fd_mfb_dst_rdy <= sp_mfb_dst_rdy;
sp_mfb_src_rdy <= fd_mfb_src_rdy;
end generate;
end generate;

-- =========================================================================
Expand Down
1 change: 1 addition & 0 deletions core/comp/eth/network_mod/Modules.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@ if {$ARCHGRP == "EMPTY"} {

# Source files for implemented component
lappend MOD "$ENTITY_BASE/qsfp_ctrl.vhd"
lappend MOD "$ENTITY_BASE/ts_sync.vhd"
lappend MOD "$ENTITY_BASE/network_mod.vhd"
lappend MOD "$ENTITY_BASE/DevTree.tcl"
}
7 changes: 7 additions & 0 deletions core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,9 @@ generic(
-- =====================================================================
-- Other configuration:
-- =====================================================================
-- Enable sharing of Ethernet TX clock. When true, the CLK_ETH_IN port is used
-- as clock source for all Eth channels
CLK_ETH_IN_ENABLE : boolean := false;
TS_DEMO_EN : boolean := false;
TX_DMA_CHANNELS : natural := 8;
-- GTY TX equalization bits: 59:40 - precursor,
Expand All @@ -79,6 +82,8 @@ port(
-- CLOCK AND RESET
-- =====================================================================
CLK_ETH : out std_logic;
CLK_ETH_IN : in std_logic := '0';
CLK_STABLE : out std_logic_vector(ETH_PORT_CHAN-1 downto 0) := (others => '1');
RESET_ETH : in std_logic;

-- =====================================================================
Expand All @@ -102,6 +107,7 @@ port(
-- =====================================================================
-- RX interface (Packets for transmit to Ethernet, recieved from MFB)
-- =====================================================================
RX_MFB_CLK : out std_logic := '0';
RX_MFB_DATA : in slv_array_t (ETH_PORT_CHAN-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
RX_MFB_SOF_POS : in slv_array_t (ETH_PORT_CHAN-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0);
RX_MFB_EOF_POS : in slv_array_t (ETH_PORT_CHAN-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0);
Expand All @@ -122,6 +128,7 @@ port(
-- =====================================================================
-- TX interface (Packets received from Ethernet, for transmit to MFB)
-- =====================================================================
TX_MFB_CLK : out std_logic_vector(ETH_PORT_CHAN-1 downto 0) := (others => '0');
TX_MFB_DATA : out slv_array_t (ETH_PORT_CHAN-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
TX_MFB_ERROR : out slv_array_t (ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
TX_MFB_SOF_POS : out slv_array_t (ETH_PORT_CHAN-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0);
Expand Down
21 changes: 12 additions & 9 deletions core/comp/eth/network_mod/comp/network_mod_logic/network_mod_logic.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ generic(
-- =====================================================================
-- OTHER configuration:
-- =====================================================================
LL_MODE : boolean := false;
RESET_USER_WIDTH : natural := 8;
-- ETH_PORT_CHAN x (TX MAC lite + RX MAC lite)
RESET_CORE_WIDTH : natural := ETH_PORT_CHAN * (1 + 1 );
Expand All @@ -73,7 +74,8 @@ port(
-- CLOCK AND RESET
-- =====================================================================
CLK_USER : in std_logic;
CLK_CORE : in std_logic;
TX_CLK_CORE : in std_logic;
RX_CLK_CORE : in std_logic_vector(ETH_PORT_CHAN-1 downto 0);

RESET_USER : in std_logic_vector(RESET_USER_WIDTH-1 downto 0);
RESET_CORE : in std_logic_vector(RESET_CORE_WIDTH-1 downto 0);
Expand Down Expand Up @@ -149,8 +151,8 @@ port(
-- =====================================================================
-- TSU interface
-- =====================================================================
TSU_TS_NS : in std_logic_vector(64-1 downto 0);
TSU_TS_DV : in std_logic
TSU_TS_NS : in slv_array_t(ETH_PORT_CHAN-1 downto 0)(64-1 downto 0);
TSU_TS_DV : in std_logic_vector(ETH_PORT_CHAN-1 downto 0)
);
end entity;

Expand Down Expand Up @@ -364,6 +366,7 @@ begin
CRC_INSERT_EN => false ,
IPG_GENERATE_EN => false ,
USE_DSP_CNT => true ,
LL_MODE => LL_MODE ,
DEVICE => DEVICE
)
port map(
Expand All @@ -389,7 +392,7 @@ begin
RX_MFB_SRC_RDY => split_mfb_src_rdy(ch),
RX_MFB_DST_RDY => split_mfb_dst_rdy(ch),

TX_CLK => CLK_CORE ,
TX_CLK => TX_CLK_CORE ,
TX_RESET => RESET_CORE(ch*2) ,
TX_MFB_DATA => TX_CORE_MFB_DATA (ch),
TX_MFB_SOF => TX_CORE_MFB_SOF (ch),
Expand Down Expand Up @@ -455,7 +458,7 @@ begin
DEVICE => DEVICE
)
port map(
RX_CLK => CLK_CORE ,
RX_CLK => RX_CLK_CORE(ch) ,
RX_RESET => RESET_CORE(ch*2+1), -- todo
TX_CLK => CLK_USER ,
TX_RESET => RESET_USER(0),
Expand All @@ -470,8 +473,8 @@ begin

ADAPTER_LINK_UP => RX_LINK_UP(ch),

TSU_TS_NS => TSU_TS_NS,
TSU_TS_DV => TSU_TS_DV,
TSU_TS_NS => TSU_TS_NS(ch),
TSU_TS_DV => TSU_TS_DV(ch),

TX_MFB_DATA => merg_mfb_data (ch),
TX_MFB_SOF => merg_mfb_sof (ch),
Expand Down Expand Up @@ -531,8 +534,8 @@ begin
MFB_ITEM_WIDTH => ITEM_WIDTH ,
INPUT_FIFO_SIZE => 8 ,
RX_PAYLOAD_EN => (others => true),
IN_PIPE_EN => true ,
OUT_PIPE_EN => true ,
IN_PIPE_EN => not LL_MODE ,
OUT_PIPE_EN => not LL_MODE ,
DEVICE => DEVICE
)
port map(
Expand Down
3 changes: 2 additions & 1 deletion core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/dut.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,8 @@ module DUT (
.BOARD (BOARD)
) VHDL_DUT_U (
.CLK_USER (CLK_USER),
.CLK_CORE (CLK_CORE),
.TX_CLK_CORE (CLK_CORE),
.RX_CLK_CORE ({ETH_CHANNELS {CLK_CORE}}),
.RESET_USER (RESET_USER),
.RESET_CORE (RESET_CORE),

Expand Down
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