Merge branch 'cabal_pcie_conf_rev' into 'devel'

Major revision of IP parameters especially PCIe

See merge request ndk/ndk-fpga!116

cards/amd/alveo-u200/src/Modules.tcl

@@ -14,22 +14,26 @@ set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top"
 # Components
 lappend COMPONENTS [list "FPGA_COMMON" $FPGA_COMMON_BASE $ARCHGRP]
 
-# IP sources
-if {$ARCHGRP_ARR(PCIE_ENDPOINTS) == 1} {
-    if {$ARCHGRP_ARR(PCIE_ENDPOINT_MODE) == 2} {
-        lappend MOD "$ENTITY_BASE/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci"
-    } else {
-        lappend MOD "$ENTITY_BASE/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci"
-    }
-}
+# IP components
+source $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/common.tcl
+
+#set ARCHGRP_ARR(IP_TEMPLATE_BASE) $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/amd
+set ARCHGRP_ARR(IP_MODIFY_BASE)   $ENTITY_BASE/ip
+set ARCHGRP_ARR(USE_IP_SUBDIRS)   true
+
+# see '$ARCHGRP_ARR(CORE_BASE)/src/ip/common.tcl' for more information regarding the fields
+#                            script_path, script_name, ip_comp_name, type, modify
+lappend IP_COMPONENTS [list "pcie" "pcie4_uscale_plus" "pcie4_uscale_plus" 0 1]
 
 if {$ARCHGRP_ARR(VIRTUAL_DEBUG_ENABLE)} {
-    lappend MOD "$ENTITY_BASE/ip/xvc_vsec/xvc_vsec.xci"
+    lappend IP_COMPONENTS [list "misc" "xvc_vsec" "xvc_vsec" 0 1]
 }
 
 if {$ARCHGRP_ARR(NET_MOD_ARCH) != "EMPTY"} {
-    lappend MOD "$ENTITY_BASE/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci"
+    lappend IP_COMPONENTS [list "eth" "cmac_eth_1x100g" "cmac_eth_1x100g" 0 1]
 }
 
+lappend MOD {*}[get_ip_mod_files $IP_COMPONENTS [array get ARCHGRP_ARR]]
+
 # Top-level
 lappend MOD "$ENTITY_BASE/fpga.vhd"

cards/amd/alveo-u200/src/Vivado.inc.tcl

@@ -27,6 +27,8 @@ set SYNTH_FLAGS(BOARD)     $CARD_NAME
 # The description of usage of this array is provided in the Parametrization section
 # of the NDK-CORE repository.
 set CARD_ARCHGRP(CORE_BASE)             $CORE_BASE
+set CARD_ARCHGRP(IP_BUILD_DIR)          $CARD_BASE/src/ip
+set CARD_ARCHGRP(IP_GEN_FILES)          false
 set CARD_ARCHGRP(PCIE_ENDPOINTS)        $PCIE_ENDPOINTS
 set CARD_ARCHGRP(PCIE_ENDPOINT_MODE)    $PCIE_ENDPOINT_MODE
 

cards/amd/alveo-u200/src/fpga.vhd

@@ -77,7 +77,6 @@ architecture FULL of FPGA is
     constant MISC_IN_WIDTH       : integer := 4;
     constant MISC_OUT_WIDTH      : integer := 4;
     constant ETH_LANES           : integer := 4;
-    constant DMA_MODULES         : integer := PCIE_ENDPOINTS;
     constant DMA_ENDPOINTS       : integer := PCIE_ENDPOINTS;
     constant ETH_LANE_MAP        : integer_vector(2*ETH_LANES-1 downto 0) := (3, 2, 1, 0, 3, 2, 1, 0);
     constant ETH_LANE_RXPOLARITY : std_logic_vector(2*ETH_LANES-1 downto 0) := "00000000";

cards/amd/alveo-u200/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.ip.tcl

@@ -0,0 +1,27 @@
+array set PARAMS $IP_PARAMS_L
+
+set IP_COMP_NAME $PARAMS(IP_COMP_NAME)
+if {[get_ips -quiet $IP_COMP_NAME] eq ""} {
+    if {$PARAMS(IP_GEN_FILES) eq true} {
+        create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME -dir $PARAMS(IP_BUILD_DIR) -force
+    } else {
+        create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME
+    }
+}
+
+set IP [get_ips $IP_COMP_NAME]
+
+set_property -dict [list \
+    CONFIG.ADD_GT_CNRL_STS_PORTS {1} \
+    CONFIG.CMAC_CAUI4_MODE {1} \
+    CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y3} \
+    CONFIG.GT_DRP_CLK {50.00} \
+    CONFIG.GT_GROUP_SELECT {X1Y20~X1Y23} \
+    CONFIG.GT_REF_CLK_FREQ {161.1328125} \
+    CONFIG.INCLUDE_RS_FEC {1} \
+    CONFIG.NUM_LANES {4x25} \
+    CONFIG.RX_FLOW_CONTROL {0} \
+    CONFIG.RX_GT_BUFFER {1} \
+    CONFIG.RX_MAX_PACKET_LEN {16383} \
+    CONFIG.TX_FLOW_CONTROL {0} \
+] $IP

cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl

@@ -0,0 +1,82 @@
+array set PARAMS $IP_PARAMS_L
+
+set IP_COMP_NAME $PARAMS(IP_COMP_NAME)
+if {[get_ips -quiet $IP_COMP_NAME] eq ""} {
+    if {$PARAMS(IP_GEN_FILES) eq true} {
+        create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME -dir $PARAMS(IP_BUILD_DIR) -force
+    } else {
+        create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME
+    }
+}
+
+set IP [get_ips $IP_COMP_NAME]
+
+# ==============================================================================
+# general settings for each card
+# ==============================================================================
+
+set VENDOR_ID {18ec}
+set PF0_DEVICE_ID {c000}
+
+# specialties for the selected card
+
+
+# ==============================================================================
+# common properties they should be the same for all cards
+# ==============================================================================
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.ext_pcie_cfg_space_enabled {true} \
+    CONFIG.extended_tag_field {true} \
+    CONFIG.plltype {QPLL1} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.AXISTEN_IF_ENABLE_CLIENT_TAG {true} \
+    CONFIG.pf0_dev_cap_max_payload {512_bytes} \
+    CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \
+    CONFIG.PF0_CLASS_CODE {020000} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {false} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {64} \
+    CONFIG.pf0_bar2_64bit {true} \
+    CONFIG.pf0_bar2_prefetchable {false} \
+    CONFIG.pf0_bar2_enabled {true} \
+    CONFIG.pf0_bar2_scale {Megabytes} \
+    CONFIG.pf0_bar2_size {16} \
+    CONFIG.pf0_rbar_cap_bar0 {0xffffffffffff} \
+    CONFIG.pf0_dsn_enabled {true} \
+    CONFIG.pf0_msi_enabled {false} \
+    CONFIG.pf0_msix_enabled {true} \
+    CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
+    CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
+    CONFIG.MSI_X_OPTIONS {MSI-X_External} \
+    CONFIG.mode_selection {Advanced} \
+    CONFIG.type1_membase_memlimit_enable {Disabled} \
+    CONFIG.type1_prefetchable_membase_memlimit {Disabled} \
+] $IP
+
+if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
+    # x8_low_latency properties
+    set_property -dict [list \
+        CONFIG.axisten_if_width {256_bit} \
+        CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+    ] $IP
+} else {
+    # x16 properties
+    set_property -dict [list \
+        CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {false} \
+        CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
+        CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+        CONFIG.axisten_if_width {512_bit} \
+        CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
+    ] $IP
+}
+
+# set PCIE IDs, must be in last set_property
+set_property -dict [list \
+    CONFIG.PF0_DEVICE_ID [subst $PF0_DEVICE_ID] \
+    CONFIG.PF0_SUBSYSTEM_ID [subst $PF0_DEVICE_ID] \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID [subst $VENDOR_ID] \
+    CONFIG.vendor_id [subst $VENDOR_ID] \
+] $IP