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release/.buildinfo

@@ -1,4 +1,4 @@
 # Sphinx build info version 1
 # This file records the configuration used when building these files. When it is not found, a full rebuild will be done.
-config: db1c1339d69cc589c6f4db3cbf231b40
+config: d9ca9643927e9f96024273c65fe247d3
 tags: 645f666f9bcd5a90fca523b33c5a78b7

release/_sources/base.rst.txt

@@ -2,7 +2,7 @@ Basic Tools
 ===========
 
 This chapter describes the basic components such as FIFOs, RAMs, multiplexers, encoders, decoders, etc.
-The basic components are typically located in the ``comp/base/`` directory in the OFM repository.
+The basic components are typically located in the ``comp/base/`` directory in the NDK-FPGA repository.
 
 .. toctree::
    :maxdepth: 1
@@ -12,6 +12,5 @@ The basic components are typically located in the ``comp/base/`` directory in th
    memory
    fifo
    dsp
-   shift
    logic
    misc

release/_sources/comp/base/mem/mem_clear/readme.rst.txt

@@ -0,0 +1,33 @@
+.. _mem_clear:
+
+Memory clear
+------------
+
+Simple component that will generate addresses for memory clearing when RST is asserted.
+
+Component port and generics description
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. vhdl:autoentity:: MEM_CLEAR
+   :noautogenerics:
+
+
+Instance template
+^^^^^^^^^^^^^^^^^
+
+.. code-block::
+
+    data_clear_i : entity work.MEM_CLEAR
+    generic map (
+        DATA_WIDTH  => BOX_WIDTH,
+        ITEMS       => BOX_CNT,
+        CLEAR_EN    => CLEAR_BY_RST
+    )
+    port map (
+        CLK         => CLK,
+        RST         => RST,
+
+        CLEAR_DONE  => RST_DONE,
+        CLEAR_WR    => wr_clear,
+        CLEAR_ADDR  => wr_addr_clear
+    );

release/_sources/comp/debug/data_logger/readme.rst.txt

@@ -171,22 +171,124 @@ Instance template (full usage)
 Control SW
 ^^^^^^^^^^
 
-Folder ``data_logger/sw/`` contains ``Python3`` package that provides:
+Folder ``data_logger/sw/`` contains following ``Python3`` packages:
 
-* Module for basic interaction with ``DATA_LOGGER``
-* Modules for ``DATA_LOGGER`` wraps like ``MEM_LOGGER``
-* Simple graph generator based on `matplotlib` library
-* Simple PDF / Markdown report generator
-* Common tools
+* ``data_logger`` ... basic interaction with ``DATA_LOGGER``
+* ``mem_logger`` ... basic interaction with ``MEM_LOGGER``
+* ``logger_stats`` ... loading firmware statistics (multiple ``DATA_LOGGERS`` can be organized in tree hierarchy)
+* ``graph_tools`` ... simple plot functions for statistics from ``logger_stats``
 
 Package can be installed using this command:
 
 * You also need to install ``python nfb`` package
 
 .. code-block::
+    python3 -m pip install --upgrade pip
 
+    # Install nfb:
+    cd swbase/pynfb
+    python3 -m pip install Cython
+    python3 -m pip install .
+    cd -
+
+    # Install this package:
     cd data_logger/sw
-    python3 setup.py install --user
+    python3 -m pip install .
+
+Example usage of ``logger_stats`` (for more usage see `mem_logger/mem_logger.py`):
+
+.. code-block::
+
+
+    import logger_stats as Stats
+    from data_logger.data_logger import DataLogger
+
+    def create_stats():
+        # Create DataLoggers
+        logger_0 = DataLogger(index=0, dev='/dev/nfb0')
+        logger_1 = DataLogger(index=1, dev='/dev/nfb0')
+
+        # Create Stats hierarchy
+        stats = Stats.LoggerStats('Example stats')
+        stats_0 = Stats.LoggerStats('Logger 0 stats', logger=logger_0)
+        stats_1 = Stats.LoggerStats('Logger 1 stats', logger=logger_1)
+        stats.add_stat(stats_0)
+        stats.add_stat(stats_1)
+
+        # Add basic statistics
+        stats_0.add_stat(Stats.Constant(index=7, name='X'))
+        stats_0.add_stat(Stats.Counter(index=7, name='Y'))
+        stats_0.add_stat(Stats.Value(index=7, name='Z'))
+
+        # FSM state statistic
+        def fms_convert(v):
+            states = [
+                'IDLE',
+                ...
+            ]
+            if v >= len(states):
+                return "???"
+            else:
+                return states[int(v)]
+
+        fsm_format = Stats.FormatDefaultValue(format=Stats.FormatNone)
+        stats_1.add_stat(Stats.Value(2, 'FSM states', convert=fms_convert, format=fsm_format))
+
+        # Latency statistic
+        FREQ = 200 * 10**6
+        time_conv = Stats.ConvertTime(FREQ)
+        time_form = Stats.FormatDefaultValue(units='ns')
+        stats_1.add_stat(Stats.Value(9, 'Latency', convert=time_conv, format=time_form))
+
+        # Add value statistic which includes multiple commands
+        CMDS = [
+            'CMD_A',
+            ...
+        ]
+        stats_1.add_stat(Stats.ValueCMD(7, 'Latency of CMDs', cmd_width=2, cmds=CMDS, convert=time_conv, format=time_form))
+
+        # Add multiple counters
+        counters = [
+            'Counter A',
+            ...
+        ]
+        stats_1.add_stats(
+            name='Counters',
+            names=counters,
+            indexes=list(range(len(counters))),
+            constructor=lambda i, n: Stats.Counter(i, n)
+        )
+
+    return stats
+
+
+    stats = create_stats()
+    stats.load()
+    print(stats.to_str())
+    stats.save('stats.npz')
+
+
+Example usage of ``graph_tools``:
+
+    from graph_tools.graph_tools import load_data, plot_counter, plot_value, plot_value_2d
+
+    stats = load_data('stats.npz')
+
+    node = pd.DataFrame.from_dict(stats['Stats A']['Counters'])
+    selected = ['Counter A', 'Counter B']
+
+    # Plot single counter
+    plot_counter(node['Counter X'], 'Time', 'Requests', 'Plot title')
+
+    # Plot multiple counters
+    plot_counter(node[selected], 'Time', 'Requests', 'Plot title')
+
+    # Plot histogram of the value interface
+    plot_value(node['Value A'], 'Time', 'Blocks', 'Title' log=True)
+
+    # Plot 2D histogram of the value interface history
+    plot_value_2d(node['Value A'], 'Time', 'Blocks', 'Title' log=True)
+
 
 
 MI address space

release/_sources/comp/mfb_tools/edit/frame_appender/readme.rst.txt

@@ -0,0 +1,12 @@
+.. readme.rst: Documentation of a single component
+.. Copyright (C) 2024 CESNET z. s. p. o.
+.. Author(s): Daniel Kondys <[email protected]>
+..
+.. SPDX-License-Identifier: BSD-3-Clause
+
+.. _mfb_mvb_appender:
+
+MFB MVB Appender
+----------------
+
+.. vhdl:autoentity:: MFB_MVB_APPENDER

release/_sources/comp/mvb_tools/flow/gate/readme.rst.txt

@@ -0,0 +1,6 @@
+.. _mvb_gate:
+
+MVB Gate
+--------
+
+.. vhdl:autoentity:: MVB_GATE

release/_sources/comp/mvb_tools/flow/item_collision_resolver/readme.rst.txt

@@ -0,0 +1,6 @@
+.. _mvb_item_collision_resolver:
+
+MVB Item Collision Resolver
+---------------------------
+
+.. vhdl:autoentity:: MVB_ITEM_COLLISION_RESOLVER

release/_sources/fifo.rst.txt

@@ -6,9 +6,17 @@ FIFO components
 Dual clock (asynchronous) FIFOs
 -------------------------------
 
-**ASFIFO** - Behavioral dual clock FIFO implementation based on LUTMEMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use ASFIFOX!``
+**ASFIFO** - Behavioral dual clock FIFO implementation, based on LUTMEMs and optimized for Xilinx only. Includes status signal.
 
-**ASFIFO_BRAM** - Behavioral dual clock FIFO implementation based on BRAMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use ASFIFOX!``
+.. warning::
+   .. deprecated:: 0.7.0
+      This component is obsolete and is a candidate for removal, use **ASFIFOX** instead.
+
+**ASFIFO_BRAM** - Behavioral dual clock FIFO implementation, based on BRAMs and optimized for Xilinx only. Includes status signal.
+
+.. warning::
+   .. deprecated:: 0.7.0
+      This component is obsolete and is a candidate for removal, use **ASFIFOX** instead.
 
 **ASFIFO_BRAM_BLOCK** - Similar to ASFIFO_BRAM but with extra signal to mark end of input data block, output remains in empty state until such mark is received. Located in the same folder as ASFIFO_BRAM.
 
@@ -34,13 +42,25 @@ Detailed :ref:`documentation can be found here<asfifox>`.
 Single clock FIFOs
 ------------------
 
-**FIFO** - Behavioral FIFO implementation based on LUTMEMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use FIFOX!``
+**FIFO** - Behavioral FIFO implementation, based on LUTMEMs and optimized for Xilinx only. Includes status signal.
+
+.. warning::
+   .. deprecated:: 0.7.0
+      This component is obsolete and is a candidate for removal, use **FIFOX** instead.
 
-**FIFO_BRAM** - Behavioral FIFO implementation based on BRAMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use FIFOX!``
+**FIFO_BRAM** - Behavioral FIFO implementation, based on BRAMs and optimized for Xilinx only. Includes status signal.
+
+.. warning::
+   .. deprecated:: 0.7.0
+      This component is obsolete and is a candidate for removal, use **FIFOX** instead.
 
 **FIFO_BRAM_XILINX** - Structural implementation of FIFO based on Xilinx specific BRAM FIFO primitives (no extra logic). Include almost full and almost empty signal.
 
-**FIFO_N1** - Behavioral implementation of FIFO with multiple write ports, it based on LUTMEMs and optimized for Xilinx only. ``OBSOLETE, use FIFOX_MULTI!``
+**FIFO_N1** - Behavioral implementation of FIFO with multiple write ports, it is based on LUTMEMs and optimized for Xilinx only.
+
+.. warning::
+   .. deprecated:: 0.7.0
+      This component is obsolete and is a candidate for removal, use **FIFOX** instead.
 
 **FIFOX** - Universal FIFO for Xilinx and Intel FPGAs. It support various memory implementation: LUTMEMs, BRAMs, URAMs (Xilinx only) and shift-registers in LUT slices (effective on Xilinx only).
 Include almost full, almost empty and status signal. Possible automatic selection of a suitable memory implementation. Detailed :ref:`documentation can be found here<fifox>`.
@@ -50,7 +70,11 @@ Include almost full, almost empty and status signal. Possible automatic selectio
 **MULTI_FIFO** - Behavioral implementation of FIFO for Xilinx and Intel FPGAs with multiple independent channels. It support various memory implementation: LUTMEMs, BRAMs, URAMs (Xilinx only).
 The memory type is selected automatically.
 
-**SH_FIFO** - Behavioral FIFO implementation based on shift-registers in LUT slices and optimized for Xilinx only. ``OBSOLETE, use FIFOX!``
+**SH_FIFO** - Behavioral FIFO implementation, based on shift-registers in LUT slices and optimized for Xilinx only.
+
+.. warning::
+   .. deprecated:: 0.7.0
+      This component is obsolete and is a candidate for removal, use **FIFOX** instead.
 
 .. toctree::
    :maxdepth: 1