Merge branch 'spinler-maint-code_style' into 'devel'

Spinler maint code style

See merge request ndk/ndk-fpga!76

.editorconfig

@@ -10,7 +10,7 @@ charset = utf-8
 indent_style = tab
 
 # Ignore section
-[*.{pcap,ip}]
+[*.{pcap,ip,qsys}]
 end_of_line = unset
 insert_final_newline = unset
 trim_trailing_whitespace = unset

VERSION

@@ -1 +1 @@
-0.7.0
+0.7.0

apps/minimal/build/dk-dev-1sdx-p/app_conf.tcl

@@ -19,7 +19,7 @@ set DMA_TX_CHANNELS      16
 # In blocking mode, packets are dropped only when the RX DMA channel is off.
 # In non-blocking mode, packets are dropped whenever they cannot be sent.
 set DMA_RX_BLOCKING_MODE true
-# Special example of 400G DMA, Ethernet is not connected to DMA and must be set 
+# Special example of 400G DMA, Ethernet is not connected to DMA and must be set
 # special PCIe config.: 2x PCIe Gen4 x8x8, requires PCIe expansion connector.
 set DMA_400G_DEMO        false
 

apps/minimal/build/pd-falcon/Makefile

@@ -22,4 +22,4 @@ all: 100g2
 100g2: OUTPUT_NAME:=$(OUTPUT_NAME)-100g2
 100g2: build
 
-include $(CARD_BASE)/src/card.mk
+include $(CARD_BASE)/src/card.mk

apps/minimal/tests/cocotb/cocotb_test.py

@@ -1,13 +1,16 @@
 import sys
 import cocotb
-import logging
-from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout
+#import logging
+from cocotb.triggers import Timer
 
 from ndk_core import NFBDevice
 
 import cocotbext.ofm.utils.sim.modelsim as ms
 import cocotb.utils
 
+from cocotbext.ofm.utils.sim.bus import MfbBus, MiBus, DmaUpMvbBus, DmaDownMvbBus
+
+
 e = cocotb.external
 st = cocotb.utils.get_sim_time
 
@@ -30,7 +33,7 @@ async def test_mi_access_unaligned(dut):
     #for i in range(46, 64): # FIXME: Test fails (for US+)
     for i in range(24, 42):
         for x in range(0, 5):
-            data = bytes([(j%256) for j in range(i)])
+            data = bytes([(j % 256) for j in range(i)])
             await e(c.write)(x, data)
             rdata = await e(c.read)(x, len(data))
             assert data == rdata, f"{list(data)}, {list(rdata)}"
@@ -85,6 +88,7 @@ async def _test_ndp_sendmsg(dut, dev=None, nfb=None):
         await e(eth.txmac.enable)()
 
     pkt = bytes([i for i in range(72)])
+
     def eth_tx_monitor_cb(p):
         print(len(p), bytes(p).hex())
         #assert bytes(p) == pkt
@@ -93,7 +97,7 @@ def eth_tx_monitor_cb(p):
 
     count = 1
     for i in range(count):
-        pkt = bytes([(i%256) for i in range(72 + i)])
+        pkt = bytes([(i % 256) for i in range(72 + i)])
         await e(nfb.ndp.tx[0].sendmsg)([(pkt, bytes(), 0)])
 
     await Timer(20, units='us')
@@ -117,7 +121,7 @@ def eth_tx_monitor_cb(p):
 
     pkts = range(20, 28)
     for i in pkts:
-        pkt = bytes([(i%256) for i in range(72 + i)])
+        pkt = bytes([(i % 256) for i in range(72 + i)])
         await e(nfb.ndp.tx[0].sendmsg)([(pkt, bytes(), 0)])
 
     await Timer(15, units='us')
@@ -134,8 +138,6 @@ async def test_ndp_send_msgs(dut):
     await _test_ndp_sendmsg_burst(dut, dev, nfb)
 
 
-from cocotbext.ofm.utils.sim.bus import *
-
 core = NFBDevice.core_instance_from_top(cocotb.top)
 
 pcic = core.pcie_i.pcie_core_i

apps/minimal/tests/cocotb/issues/issue1.py

@@ -1,14 +1,10 @@
-import sys
-import logging
-
 import cocotb
 import cocotb.utils
-from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout
+from cocotb.triggers import Timer, RisingEdge, First
 
-import cocotbext.ofm.utils.sim.modelsim as ms
 import cocotbext.ofm.utils.sim.modelsim as ms
 
-from cocotbext.ofm.utils.sim.bus import *
+from cocotbext.ofm.utils.sim.bus import MfbBus, DmaDownMvbBus
 from cocotbext.ofm.utils.scapy import simple_tcp_bytes
 
 from ndk_core import NFBDevice

apps/minimal/tests/cocotb/issues/issue2.py

@@ -1,14 +1,9 @@
-import sys
-import logging
-
 import cocotb
 import cocotb.utils
-from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout
 
 import cocotbext.ofm.utils.sim.modelsim as ms
 
-from cocotbext.ofm.utils.sim.bus import *
-from cocotbext.ofm.utils.scapy import simple_tcp_bytes
+from cocotbext.ofm.utils.sim.bus import MiBus
 
 from ndk_core import NFBDevice
 
@@ -17,21 +12,23 @@
 e = cocotb.external
 st = cocotb.utils.get_sim_time
 
+
 def ms_add_cursor(name, time=None):
     if time is None:
         time = st()
 
-    ms.cmd(f"wave cursor add")
+    ms.cmd("wave cursor add")
     ms.cmd(f'wave cursor configure -name {{{name}}} -time {{{time}}} -lock 1')
 
+
 async def get_dev_init(dut):
     dev = NFBDevice(dut)
     await dev.init()
     return dev, dev.nfb
 
 
 async def wr_rd(c, length, offset=0):
-    data = bytes([(j%256) for j in range(length)])
+    data = bytes([(j % 256) for j in range(length)])
     await e(c.write)(offset, data)
     rdata = await e(c.read)(offset, length)
     assert rdata == data, f'writen: {list(data)}, readen: {list(rdata)}'
@@ -45,10 +42,6 @@ async def mtc_big_write_tr(dut):
     await wr_rd(c, 126, 3)
 
 
-
-
-
-
 core = NFBDevice.core_instance_from_top(cocotb.top)
 core_path = ms.cocotb2path(core)
 

apps/minimal/top/app_subcore.vhd

@@ -42,11 +42,11 @@ port (
     -- =========================================================================
     CLK      : in  std_logic;
     RESET    : in  std_logic;
-    
+
     -- =========================================================================
     --  DMA INTERFACES
     -- =========================================================================
-    
+
     -- MFB+MVB interface to DMA module (to software)
     -- -------------------------------------------------------------------------
     DMA_RX_MVB_LEN           : out std_logic_vector(MFB_REGIONS*log2(USR_PKT_SIZE_MAX+1)-1 downto 0);
@@ -65,7 +65,7 @@ port (
     DMA_RX_MFB_EOF_POS       : out std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0);
     DMA_RX_MFB_SRC_RDY       : out std_logic;
     DMA_RX_MFB_DST_RDY       : in  std_logic;
-    
+
     -- MFB+MVB interface from DMA module (from software)
     -- -------------------------------------------------------------------------
     -- MVB interface (aligned to SOF)
@@ -89,7 +89,7 @@ port (
     -- =========================================================================
     --  ETH INTERFACES
     -- =========================================================================
-    
+
     -- MFB+MVB interface with incoming network packets
     -- -------------------------------------------------------------------------
     -- MVB interface with packet headers (aligned to EOF)
@@ -117,7 +117,7 @@ port (
     ETH_TX_MFB_EOF_POS      : out std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0);
     ETH_TX_MFB_SRC_RDY      : out std_logic;
     ETH_TX_MFB_DST_RDY      : in  std_logic;
-    
+
     -- =========================================================================
     --  MI INTERFACE
     -- =========================================================================
@@ -222,15 +222,15 @@ begin
         RX_MVB_VLD      => DMA_TX_MVB_VLD,
         RX_MVB_SRC_RDY  => DMA_TX_MVB_SRC_RDY,
         RX_MVB_DST_RDY  => DMA_TX_MVB_DST_RDY,
-    
+
         RX_MFB_DATA     => DMA_TX_MFB_DATA,
         RX_MFB_SOF      => DMA_TX_MFB_SOF,
         RX_MFB_EOF      => DMA_TX_MFB_EOF,
         RX_MFB_SOF_POS  => DMA_TX_MFB_SOF_POS,
         RX_MFB_EOF_POS  => DMA_TX_MFB_EOF_POS,
         RX_MFB_SRC_RDY  => DMA_TX_MFB_SRC_RDY,
         RX_MFB_DST_RDY  => DMA_TX_MFB_DST_RDY,
-    
+
         TX_MFB_DATA     => ethi_tx_mfb_data,
         TX_MFB_META_NEW => ethi_tx_mfb_hdr,
         TX_MFB_SOF      => ethi_tx_mfb_sof,

apps/minimal/top/application_core.vhd

@@ -135,7 +135,7 @@ architecture FULL of APPLICATION_CORE is
     signal split_mi_wr                   : std_logic_vector(MI_PORTS-1 downto 0);
     signal split_mi_ardy                 : std_logic_vector(MI_PORTS-1 downto 0) := (others => '0');
     signal split_mi_drd                  : slv_array_t     (MI_PORTS-1 downto 0)(MI_DATA_WIDTH-1 downto 0);
-    signal split_mi_drdy                 : std_logic_vector(MI_PORTS-1 downto 0) := (others => '0');   
+    signal split_mi_drdy                 : std_logic_vector(MI_PORTS-1 downto 0) := (others => '0');
 
 begin
 
@@ -210,7 +210,7 @@ begin
     port map(
         CLK        => APP_CLK,
         RESET      => APP_RESET(0),
-        
+
         RX_DWR     => sync_mi_dwr,
         RX_ADDR    => sync_mi_addr,
         RX_BE      => sync_mi_be,
@@ -301,7 +301,7 @@ begin
             DMA_TX_MFB_EOF_POS      => app_dma_tx_mfb_eof_pos_deser(i),
             DMA_TX_MFB_SRC_RDY      => app_dma_tx_mfb_src_rdy_deser(i),
             DMA_TX_MFB_DST_RDY      => app_dma_tx_mfb_dst_rdy_deser(i),
-        
+
             ETH_RX_MVB_DATA         => eth_rx_mvb_data_deser(i),
             ETH_RX_MVB_VLD          => eth_rx_mvb_vld_deser(i),
             ETH_RX_MVB_SRC_RDY      => ETH_RX_MVB_SRC_RDY(i),
@@ -314,7 +314,7 @@ begin
             ETH_RX_MFB_EOF_POS      => eth_rx_mfb_eof_pos_deser(i),
             ETH_RX_MFB_SRC_RDY      => ETH_RX_MFB_SRC_RDY(i),
             ETH_RX_MFB_DST_RDY      => ETH_RX_MFB_DST_RDY(i),
-        
+
             ETH_TX_MFB_DATA         => eth_tx_mfb_data_deser(i),
             ETH_TX_MFB_HDR          => eth_tx_mfb_hdr_deser(i),
             ETH_TX_MFB_SOF          => eth_tx_mfb_sof_deser(i),
@@ -323,7 +323,7 @@ begin
             ETH_TX_MFB_EOF_POS      => eth_tx_mfb_eof_pos_deser(i),
             ETH_TX_MFB_SRC_RDY      => ETH_TX_MFB_SRC_RDY(i),
             ETH_TX_MFB_DST_RDY      => ETH_TX_MFB_DST_RDY(i),
-            
+
             MI_DWR                  => split_mi_dwr(i),
             MI_ADDR                 => split_mi_addr(i),
             MI_BE                   => split_mi_be(i),
@@ -538,7 +538,7 @@ begin
         HBM_AXI_BRESP          => HBM_AXI_BRESP,
         HBM_AXI_BVALID         => HBM_AXI_BVALID,
         HBM_AXI_BREADY         => HBM_AXI_BREADY,
-    
+
         DDR_CLK                => MEM_CLK,
         DDR_RESET              => MEM_RST,
         DDR_AVMM_READY         => MEM_AVMM_READY,
@@ -558,7 +558,7 @@ begin
         EMIF_CAL_SUCCESS       => EMIF_CAL_SUCCESS,
         EMIF_CAL_FAIL          => EMIF_CAL_FAIL,
         EMIF_AUTO_PRECHARGE    => EMIF_AUTO_PRECHARGE,
-    
+
         MI_DWR                 => split_mi_dwr(ETH_STREAMS),
         MI_ADDR                => split_mi_addr(ETH_STREAMS),
         MI_BE                  => split_mi_be(ETH_STREAMS),

apps/minimal/top/mem_tester_wrap.vhd

@@ -60,7 +60,7 @@ port (
     -- =========================================================================
     CLK      : in  std_logic;
     RESET    : in  std_logic;
-    
+
     -- =========================================================================
     -- HBM AXI INTERFACES (clocked at HBM_CLK)
     -- =========================================================================
@@ -217,7 +217,7 @@ begin
     port map(
         CLK        => CLK,
         RESET      => RESET,
-        
+
         RX_DWR     => MI_DWR,
         RX_ADDR    => MI_ADDR,
         RX_BE      => MI_BE,
@@ -251,7 +251,7 @@ begin
 
             MI_DATA_WIDTH               => MI_DATA_WIDTH,
             MI_ADDR_WIDTH               => MI_ADDR_WIDTH,
-     
+
             RAND_GEN_DATA_WIDTH         => MT_RND_GEN_DATA_WIDTH,
             RAND_GEN_ADDR_WIDTH         => MT_RND_GEN_ADDR_WIDTH,
             RANDOM_DATA_SEED            => ddr_random_data_seed_f,
@@ -267,7 +267,7 @@ begin
         port map(
             AMM_CLK                     => DDR_CLK                  (i),
             AMM_RST                     => DDR_RESET                (i),
-     
+
             AMM_READY                   => DDR_AVMM_READY           (i),
             AMM_READ                    => DDR_AVMM_READ            (i),
             AMM_WRITE                   => DDR_AVMM_WRITE           (i),
@@ -287,8 +287,8 @@ begin
             EMIF_CAL_SUCCESS            => EMIF_CAL_SUCCESS         (i),
             EMIF_CAL_FAIL               => EMIF_CAL_FAIL            (i),
             EMIF_AUTO_PRECHARGE         => EMIF_AUTO_PRECHARGE      (i),
-     
-            MI_CLK                      => CLK, 
+
+            MI_CLK                      => CLK,
             MI_RST                      => RESET,
             MI_DWR                      => split_mi_dwr             (i),
             MI_ADDR                     => split_mi_addr            (i),
@@ -331,18 +331,18 @@ begin
         );
 
         ddr_logger_i : entity work.MEM_LOGGER
-        generic map (    
+        generic map (
             MEM_DATA_WIDTH          => DDR_DATA_WIDTH       ,
             MEM_ADDR_WIDTH          => DDR_ADDR_WIDTH       ,
             MEM_BURST_COUNT_WIDTH   => DDR_BURST_WIDTH      ,
             MEM_FREQ_KHZ            => DDR_FREQ_KHZ         ,
             MI_DATA_WIDTH           => MI_DATA_WIDTH        ,
             MI_ADDR_WIDTH           => MI_ADDR_WIDTH
         )
-        port map (    
+        port map (
             CLK                     => DDR_CLK                  (i),
             RST                     => DDR_RESET                (i),
-        
+
             MEM_READY               => DDR_AVMM_READY           (i),
             MEM_READ                => DDR_AVMM_READ            (i),
             MEM_WRITE               => DDR_AVMM_WRITE           (i),
@@ -351,7 +351,7 @@ begin
             MEM_WRITE_DATA          => DDR_AVMM_WRITEDATA       (i),
             MEM_BURST_COUNT         => DDR_AVMM_BURSTCOUNT      (i),
             MEM_READ_DATA_VALID     => DDR_AVMM_READDATAVALID   (i),
-        
+
             MI_DWR                  => ddr_log_mi_dwr           (i),
             MI_ADDR                 => ddr_log_mi_addr          (i),
             MI_BE                   => ddr_log_mi_be            (i),

apps/minimal/uvm/env/model.sv

@@ -1,7 +1,7 @@
 /*
  * file       : model_minimal.sv
  * Copyright (C) 2021 CESNET z. s. p. o.
- * description: Model create expectated output from input. 
+ * description: Model create expectated output from input.
  * date       : 2021
  * author     : Radek Iša <[email protected]>
  *
@@ -65,7 +65,7 @@ class model #(ETH_STREAMS, ETH_CHANNELS, ETH_RX_HDR_WIDTH, DMA_STREAMS, DMA_RX_C
 
             packet = uvm_app_core::packet #(DMA_HDR_META_WIDTH, DMA_RX_CHANNELS, DMA_PKT_MTU, ITEM_WIDTH)::type_id::create("packet", this);
             packet.start = item.start;
-            packet.data = item.data; 
+            packet.data = item.data;
             packet.meta = '0;
             if (DMA_STREAMS != ETH_STREAMS) begin
                 packet.channel = (index*APP_RX_CHANNELS) + eth_to_dma[index].port_get(item.channel%ETH_CHANNELS);
@@ -98,7 +98,7 @@ class model #(ETH_STREAMS, ETH_CHANNELS, ETH_RX_HDR_WIDTH, DMA_STREAMS, DMA_RX_C
             packet = uvm_app_core::packet #(0, 2**ETH_TX_CHANNEL_WIDTH, 2**ETH_TX_LENGTH_WIDTH-1, ITEM_WIDTH)::type_id::create("packet", this);
             packet.start = item.start;
             eth_channel = ((index * DMA_TX_CHANNELS) + item.channel)/((DMA_STREAMS*DMA_TX_CHANNELS)/(ETH_STREAMS*ETH_CHANNELS));
-            packet.channel = eth_channel; 
+            packet.channel = eth_channel;
             packet.discard = 1'b0;
             packet.data  = item.data;
 

apps/minimal/uvm/test_pkg.sv

@@ -1,7 +1,7 @@
 /*
  * file       : test_pkg.sv
  * Copyright (C) 2021 CESNET z. s. p. o.
- * description: DUT configuration file. This file contains top level generic paramet 
+ * description: DUT configuration file. This file contains top level generic paramet
  * date       : 2021
  * author     : Radek Iša <[email protected]>
  *