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Unexpected transaction are generated after pcie reset on DMA DOWN MVB/MFB
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Original file line number | Diff line number | Diff line change |
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import sys | ||
import logging | ||
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import cocotb | ||
import cocotb.utils | ||
from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout | ||
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import cocotbext.ofm.utils.sim.modelsim as ms | ||
import cocotbext.ofm.utils.sim.modelsim as ms | ||
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from cocotbext.ofm.utils.sim.bus import * | ||
from cocotbext.ofm.utils.scapy import simple_tcp_bytes | ||
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from ndk_core import NFBDevice | ||
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print = ms.print | ||
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e = cocotb.external | ||
st = cocotb.utils.get_sim_time | ||
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core = NFBDevice.core_instance_from_top(cocotb.top) | ||
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async def get_dev_init(dut): | ||
dev = NFBDevice(dut) | ||
await dev.init() | ||
return dev, dev.nfb | ||
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async def _rx_pkts(dev, nfb): | ||
for eth in nfb.eth: | ||
await e(eth.rxmac.enable)() | ||
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await e(nfb.ndp.rx[0].start)() | ||
await dev.dma.rx[0]._push_desc() | ||
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await Timer(2, units='us') | ||
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pkt = simple_tcp_bytes() | ||
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for i in range(10): | ||
await dev._eth_rx_driver[0].write_packet(list(pkt)) | ||
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@cocotb.test() | ||
async def reset_pci_inside_pkt_rx(dut): | ||
dev, nfb = await get_dev_init(dut) | ||
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for eth in nfb.eth: | ||
await e(eth.rxmac.enable)() | ||
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await _rx_pkts(dev, nfb) | ||
await dev._reset() | ||
await _rx_pkts(dev, nfb) | ||
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pci_core = core.pcie_i.pcie_core_i | ||
ms.cmd(f"log -recursive {ms.cocotb2path(core)}/*") | ||
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ms.add_wave(core.global_reset) | ||
ms.add_wave(pci_core.PCIE_USER_RESET) | ||
ms.add_wave(pci_core.PCIE_USER_CLK) | ||
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ms.add_wave(core.pcie_i.MI_CLK) | ||
ms.add_wave(core.pcie_i.MI_RESET) | ||
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#ms.add_wave(core.dma_i.MI_CLK) | ||
#ms.add_wave(core.dma_i.MI_RESET) | ||
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ms.add_wave(core.dma_i.DMA_CLK) | ||
ms.add_wave(core.dma_i.DMA_RESET) | ||
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ms.add_wave(core.dma_i.USR_CLK) | ||
ms.add_wave(core.dma_i.USR_RESET) | ||
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#ms.add_wave(core.dma_i.CROX_CLK) | ||
#ms.add_wave(core.dma_i.CROX_RESET) | ||
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MfbBus(core.dma_i, 'RX_USR_MFB', 0, label='DMA RX_MFB').add_wave() | ||
#MfbBus(core.dma_i, 'TX_USR_MFB', 0).add_wave() | ||
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#DmaUpMvbBus(core.dma_i, 'PCIE_RQ_MVB', 0).add_wave() | ||
#MfbBus(core.dma_i, 'PCIE_RQ_MFB', 0).add_wave() | ||
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DmaDownMvbBus(core.dma_i, 'PCIE_RC_MVB', 0).add_wave() | ||
MfbBus(core.dma_i, 'PCIE_RC_MFB', 0).add_wave() | ||
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#MfbBus(pci_core, 'RC_MFB', 0).add_wave() | ||
#MfbBus(pci_core, 'RQ_MFB', 0).add_wave() | ||
#MfbBus(pci_core, 'CC_MFB', 0).add_wave() | ||
#MfbBus(pci_core, 'CQ_MFB', 0).add_wave() |
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