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devel/_sources/comp/axis_tools/storage/asfifox/readme.rst.txt
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.. _axis_asfifox: | ||
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AXIS_ASFIFOX | ||
------------ | ||
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.. vhdl:autoentity:: AXIS_ASFIFOX |
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<section id="axis-asfifox"> | ||
<span id="id1"></span><h1>AXIS_ASFIFOX<a class="headerlink" href="#axis-asfifox" title="Link to this heading"></a></h1> | ||
<dl class="vhdl autoentity"> | ||
<dt class="sig sig-object vhdl" id="vhdl-entity-axis_asfifox"> | ||
<span class="k"><span class="pre">ENTITY</span> </span><span class="sig-name descname"><span class="pre">AXIS_ASFIFOX</span></span><span class="k"> <span class="pre">IS</span></span><a class="headerlink" href="#vhdl-entity-axis_asfifox" title="Link to this definition"></a></dt> | ||
<dd><span class="sig-name descname">Generics</span><table class="docutils align-default"> | ||
<thead> | ||
<tr class="row-odd"><th class="head"><p>Generic</p></th> | ||
<th class="head"><p>Type</p></th> | ||
<th class="head"><p>Default</p></th> | ||
<th class="head"><p>Description</p></th> | ||
</tr> | ||
</thead> | ||
<tbody> | ||
<tr class="row-even" id="vhdl-gengeneric-axis_asfifox-tdata_width"><td><p>TDATA_WIDTH</p></td> | ||
<td><p>natural</p></td> | ||
<td><p>512</p></td> | ||
<td><p>Width of AXI-Stream data signal in bits.</p></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-gengeneric-axis_asfifox-tuser_width"><td><p>TUSER_WIDTH</p></td> | ||
<td><p>natural</p></td> | ||
<td><p>64</p></td> | ||
<td><p>Width of AXI-Stream user signal in bits.</p></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-gengeneric-axis_asfifox-fifo_items"><td><p>FIFO_ITEMS</p></td> | ||
<td><p>natural</p></td> | ||
<td><p>512</p></td> | ||
<td><p>FIFO depth in number of data words, must be power of two! | ||
Minimum value is 2.</p></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-gengeneric-axis_asfifox-ram_type"><td><p>RAM_TYPE</p></td> | ||
<td><p>string</p></td> | ||
<td><p>“BRAM”</p></td> | ||
<td><p>Select memory implementation. Options: | ||
“LUT” - effective for shallow FIFO (approx. ITEMS <= 64), | ||
“BRAM” - effective for deep FIFO (approx. ITEMS > 64).</p></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-gengeneric-axis_asfifox-fwft_mode"><td><p>FWFT_MODE</p></td> | ||
<td><p>boolean</p></td> | ||
<td><p>True</p></td> | ||
<td><p>First Word Fall Through mode. If FWFT_MODE=True, valid data will be | ||
ready at the ASFIFOX output without TX_AXIS_TREADY requests.</p></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-gengeneric-axis_asfifox-output_reg"><td><p>OUTPUT_REG</p></td> | ||
<td><p>boolean</p></td> | ||
<td><p>True</p></td> | ||
<td><p>Enabled output registers allow better timing for a few flip-flops.</p></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-gengeneric-axis_asfifox-afull_offset"><td><p>AFULL_OFFSET</p></td> | ||
<td><p>natural</p></td> | ||
<td><p>FIFO_ITEMS/2</p></td> | ||
<td><p>Sets the maximum number of remaining free data words in the ASFIFOX | ||
that triggers the RX_FIFO_AFULL signal.</p></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-gengeneric-axis_asfifox-aempty_offset"><td><p>AEMPTY_OFFSET</p></td> | ||
<td><p>natural</p></td> | ||
<td><p>FIFO_ITEMS/2</p></td> | ||
<td><p>Sets the maximum number of data words stored in the ASFIFOX that | ||
triggers the TX_FIFO_AEMPTY signal.</p></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-gengeneric-axis_asfifox-device"><td><p>DEVICE</p></td> | ||
<td><p>string</p></td> | ||
<td><p>“AGILEX”</p></td> | ||
<td><p>Target device: AGILEX, STRATIX10, ULTRASCALE,…</p></td> | ||
</tr> | ||
</tbody> | ||
</table> | ||
<span class="sig-name descname">Ports</span><table class="docutils align-default"> | ||
<thead> | ||
<tr class="row-odd"><th class="head"><p>Port</p></th> | ||
<th class="head"><p>Type</p></th> | ||
<th class="head"><p>Mode</p></th> | ||
<th class="head"><p>Description</p></th> | ||
</tr> | ||
</thead> | ||
<tbody> | ||
<tr class="row-even"><td><p>=====</p></td> | ||
<td><p>RX AXI-Stream interface (RX_CLK)</p></td> | ||
<td><p>=====</p></td> | ||
<td><p>=====</p></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-rx_clk"><td><p>RX_CLK</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-rx_reset"><td><p>RX_RESET</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-rx_axis_tdata"><td><p>RX_AXIS_TDATA</p></td> | ||
<td><p>std_logic_vector(TDATA_WIDTH-1 downto 0)</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-rx_axis_tuser"><td><p>RX_AXIS_TUSER</p></td> | ||
<td><p>std_logic_vector(TUSER_WIDTH-1 downto 0)</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-rx_axis_tkeep"><td><p>RX_AXIS_TKEEP</p></td> | ||
<td><p>std_logic_vector(TDATA_WIDTH/8-1 downto 0)</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-rx_axis_tlast"><td><p>RX_AXIS_TLAST</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-rx_axis_tvalid"><td><p>RX_AXIS_TVALID</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-rx_axis_tready"><td><p>RX_AXIS_TREADY</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-rx_fifo_afull"><td><p>RX_FIFO_AFULL</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-rx_fifo_status"><td><p>RX_FIFO_STATUS</p></td> | ||
<td><p>std_logic_vector(log2(FIFO_ITEMS) downto 0)</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd"><td><p>=====</p></td> | ||
<td><p>TX AXI-Stream interface (TX_CLK)</p></td> | ||
<td><p>=====</p></td> | ||
<td><p>=====</p></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-tx_clk"><td><p>TX_CLK</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-tx_reset"><td><p>TX_RESET</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-tx_axis_tdata"><td><p>TX_AXIS_TDATA</p></td> | ||
<td><p>std_logic_vector(TDATA_WIDTH-1 downto 0)</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-tx_axis_tuser"><td><p>TX_AXIS_TUSER</p></td> | ||
<td><p>std_logic_vector(TUSER_WIDTH-1 downto 0)</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-tx_axis_tkeep"><td><p>TX_AXIS_TKEEP</p></td> | ||
<td><p>std_logic_vector(TDATA_WIDTH/8-1 downto 0)</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-tx_axis_tlast"><td><p>TX_AXIS_TLAST</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-tx_axis_tvalid"><td><p>TX_AXIS_TVALID</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-tx_axis_tready"><td><p>TX_AXIS_TREADY</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>in</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-even" id="vhdl-portsignal-axis_asfifox-tx_fifo_aempty"><td><p>TX_FIFO_AEMPTY</p></td> | ||
<td><p>std_logic</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
<tr class="row-odd" id="vhdl-portsignal-axis_asfifox-tx_fifo_status"><td><p>TX_FIFO_STATUS</p></td> | ||
<td><p>std_logic_vector(log2(FIFO_ITEMS) downto 0)</p></td> | ||
<td><p>out</p></td> | ||
<td></td> | ||
</tr> | ||
</tbody> | ||
</table> | ||
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