Merge branch 'hak-feat-ia440i' into 'devel'

feat(cards): add basic support for Bittware IA-440i card

See merge request ndk/ndk-fpga!107

apps/minimal/build/ia-440i/Makefile

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+# Makefile: Makefile for card
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#            Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: Usage of the configuration parameters in this file is described
+# in the Parametrization section of the NDK-CORE documentation.
+
+# Set path to top-level of NDK-FPGA repository
+COMBO_BASE = ../../../..
+CARD_BASE = $(COMBO_BASE)/cards/bittware/ia-440i
+APP_CONF = app_conf.tcl
+OUTPUT_NAME = ia-440i-minimal
+
+.PHONY: all 400g1 # 100g2 25g8 10g8
+
+all: 400g1
+
+# TODO: add support for different ETH configurations
+# 10g8: ETH_PORT_SPEED=10
+# 10g8: ETH_PORT_CHAN=4
+# 10g8: OUTPUT_NAME:=$(OUTPUT_NAME)-10g8
+# 10g8: build
+#
+# 25g8: ETH_PORT_SPEED=25
+# 25g8: ETH_PORT_CHAN=4
+# 25g8: OUTPUT_NAME:=$(OUTPUT_NAME)-25g8
+# 25g8: build
+#
+# 100g2: ETH_PORT_SPEED=100
+# 100g2: ETH_PORT_CHAN=1
+# 100g2: OUTPUT_NAME:=$(OUTPUT_NAME)-100g2
+# 100g2: build
+
+400g1: ETH_PORT_SPEED=400
+400g1: ETH_PORT_CHAN=1
+400g1: EHIP_PORT_TYPE=0
+400g1: OUTPUT_NAME:=$(OUTPUT_NAME)-400g1
+400g1: build
+
+include $(CARD_BASE)/src/card.mk

apps/minimal/build/ia-440i/Quartus.tcl

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+# Quartus.tcl: Quartus tcl script to compile whole FPGA design
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#            Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: The purpose of this file is described in the Parameterization section of
+# the NDK-CORE documentation.
+
+# ----- Setting basic synthesis options ---------------------------------------
+# NDK & user constants
+source $env(CARD_BASE)/src/Quartus.inc.tcl
+
+# Create only a Quartus project for further design flow driven from Quartus GUI
+# "0" ... full design flow in command line
+# "1" ... project composition only for further dedesign flow in GUI
+set SYNTH_FLAGS(PROJ_ONLY) "0"
+
+# Associative array which is propagated to APPLICATION_CORE, add other
+# parameters if necessary.
+set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE
+
+# Convert associative array to list
+set APP_ARCHGRP_L [array get APP_ARCHGRP]
+
+# ----- Add application core to main component list ---------------------------
+lappend HIERARCHY(COMPONENTS) \
+    [list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L]
+
+# Call main function which handle targets
+nb_main

apps/minimal/build/ia-440i/app_conf.tcl

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+# app_conf.tcl: User parameters for card
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#            Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: The detailed description of the usage of this file can be viewed in the
+# Parametrizing section of the NDK-CORE documentation.
+
+# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration.
+
+# ------------------------------------------------------------------------------
+# DMA parameters:
+# ------------------------------------------------------------------------------
+# The minimum number of RX/TX DMA channels for this card is 16.
+set DMA_RX_CHANNELS      16
+set DMA_TX_CHANNELS      16
+# In blocking mode, packets are dropped only when the RX DMA channel is off.
+# In non-blocking mode, packets are dropped whenever they cannot be sent.
+set DMA_RX_BLOCKING_MODE true
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set PROJECT_NAME "NDK_MINIMAL"
+set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS"
+set PROJECT_VERSION [exec cat ../../../../VERSION]

cards/bittware/ia-440i/config/card_conf.tcl

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+# card_conf.tcl: User configurable for card
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#            Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: For the detailed description of this file, visit the Parametrization section
+# in the documentation of the NDK-CORE repository.
+
+set PROJECT_NAME ""
+
+# ------------------------------------------------------------------------------
+# ETH parameters:
+# ------------------------------------------------------------------------------
+# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED!
+set ETH_PORTS         1
+# Speed for each one of the ETH_PORTS
+# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and
+# each index has associated a required port speed.
+# NOTE: at this moment, all ports must have same speed !
+set ETH_PORT_SPEED(0) $env(ETH_PORT_SPEED)
+# Number of channels for each one of the ETH_PORTS
+# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and
+# each index has associated a required number of channels this port has.
+# NOTE: at this moment, all ports must have same number of channels !
+set ETH_PORT_CHAN(0) $env(ETH_PORT_CHAN)
+# Number of lanes for each one of the ETH_PORTS
+# Typical values: 4 (QSFP), 8 (QSFP-DD)
+set ETH_PORT_LANES(0) 8
+# EHIP_PORT_TYPE is an array where each index represents given ETH_PORT and
+# each index has associated a required type of IP core, which this port has.
+# NOTE: at this moment, all ports must have same type of IP core !
+set EHIP_PORT_TYPE(0)  $env(EHIP_PORT_TYPE)
+
+# ------------------------------------------------------------------------------
+# PCIe parameters (not all combinations work):
+# ------------------------------------------------------------------------------
+# Supported combinations for this card:
+# 1x PCIe Gen5 x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: default configuration)
+# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1
+# ------------------------------------------------------------------------------
+
+# Set default PCIe configuration
+set PCIE_CONF "1xGen5x16"
+if { [info exist env(PCIE_CONF)] } {
+    set PCIE_CONF $env(PCIE_CONF)
+}
+
+# Parsing PCIE_CONF string to list of parameters
+set pcie_conf_list [ParsePcieConf $PCIE_CONF]
+
+# PCIe Generation:
+# 4 = PCIe Gen4 (Stratix 10 with P-Tile or Agilex)
+set PCIE_GEN           [lindex $pcie_conf_list 1]
+# PCIe endpoints:
+# 1 = 1x PCIe x16 in one slot
+# 2 = 2x PCIe x8 in one slot (bifurcation x8+x8)
+set PCIE_ENDPOINTS     [lindex $pcie_conf_list 0]
+# PCIe endpoint mode:
+# 0 = 1x16 lanes
+# 1 = 2x8 lanes (bifurcation x8+x8)
+set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2]
+
+# ------------------------------------------------------------------------------
+# DMA parameters:
+# ------------------------------------------------------------------------------
+# This variable can be set in COREs *.mk file or as a parameter when launching the make
+set DMA_TYPE             $env(DMA_TYPE)
+# The minimum number of RX/TX DMA channels for this card is 16.
+set DMA_RX_CHANNELS      16
+set DMA_TX_CHANNELS      16
+# In blocking mode, packets are dropped only when the RX DMA channel is off.
+# In non-blocking mode, packets are dropped whenever they cannot be sent.
+set DMA_RX_BLOCKING_MODE true
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set TSU_ENABLE true
+
+# ------------------------------------------------------------------------------
+# DDR4 parameters:
+# ------------------------------------------------------------------------------
+set MEM_PORTS 0

cards/bittware/ia-440i/config/card_const.tcl

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+# card_const.tcl: Default parameters for card
+# Copyright (C) 2024 CESNET, z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#            Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# WARNING: The user should not deliberately change parameters in this file. For
+# the description of this file, visit the Parametrization section in the
+# documentation of the NDK-CORE repostiory
+
+set CARD_NAME "IA-440I"
+# Achitecture of Clock generator (INTEL or USP)
+set CLOCK_GEN_ARCH "INTEL"
+# Achitecture of PCIe module (P_TILE, R_TILE or USP)
+set PCIE_MOD_ARCH "R_TILE"
+# Achitecture of Network module (E_TILE, F_TILE, CMAC or EMPTY)
+set NET_MOD_ARCH "F_TILE"
+# Achitecture of SDM/SYSMON module
+set SDM_SYSMON_ARCH "INTEL_SDM"
+# Boot controller type
+set BOOT_TYPE 0
+# Total number of DMA modules/streams in FW
+set DMA_MODULES 1
+
+# Total number of QSFP cages
+set QSFP_CAGES 1
+# I2C address of each QSFP cage
+set QSFP_I2C_ADDR(0) "0xA0"
+
+# ------------------------------------------------------------------------------
+# Checking of parameter compatibility
+# ------------------------------------------------------------------------------
+
+if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
+      ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1)) } {
+    error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
+Allowed PCIe configurations:
+- 1xGen5x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0
+- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1"
+}
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+
+if {$ETH_PORT_SPEED(0) == 10 || $ETH_PORT_SPEED(0) == 25 || $ETH_PORT_SPEED(0) == 40} {
+    # TBD lower frequency for 10GE, 40GE?
+    #set TSU_FREQUENCY 161132812
+    # Current setup:
+    # 10GE, 25GE, 40GE in F-Tile
+    set TSU_FREQUENCY 402832031
+} else {
+    # 400GE, 200GE, 100GE, 50GE in F-Tile
+    set TSU_FREQUENCY 415039062
+}

cards/bittware/ia-440i/constr/bmc.qsf

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+# bmc.qsf
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# ==============================================================================
+# Board Management Controller (BMC) Interface
+# ==============================================================================
+
+set_location_assignment PIN_DA17 -to FPGA_EG_SPI_SCK
+set_location_assignment PIN_CY18 -to FPGA_EG_SPI_MISO
+set_location_assignment PIN_CN19 -to FPGA_EG_SPI_MOSI
+set_location_assignment PIN_CM20 -to FPGA_EG_SPI_PCS0
+set_location_assignment PIN_CC19 -to BMC_TO_FPGA_IRQ
+
+set_location_assignment PIN_CR19 -to FPGA_IG_SPI_SCK
+set_location_assignment PIN_CT20 -to FPGA_IG_SPI_MISO
+set_location_assignment PIN_CN21 -to FPGA_IG_SPI_MOSI
+set_location_assignment PIN_CM22 -to FPGA_IG_SPI_PCS0
+set_location_assignment PIN_CG23 -to FPGA_TO_BMC_IRQ
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to FPGA_IG_SPI_MISO
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to FPGA_IG_SPI_MOSI
+
+set_location_assignment PIN_CH24 -to BMC_IF_PRESENT_N
+
+# BMC_GPIO0 and BMC_GPIO1 are RESERVED for future use
+# BMC_GPIO0 - General purpose output from the FPGA to the BMC
+# BMC_GPIO1 - General purpose input from the BMC to the FPGA
+# set_location_assignment PIN_CU21 -to BMC_GPIO0
+# set_location_assignment PIN_CV22 -to BMC_GPIO1
+
+# Reset from the BMC - independent from the BMC interface
+set_location_assignment PIN_CL23 -to BMC_RST_N

cards/bittware/ia-440i/constr/general.qsf

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+# general.qsf
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#            Tomas Hak <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# ==============================================================================
+# Main device/configuration
+# ==============================================================================
+
+set_global_assignment -name FAMILY "Agilex 7"
+set_global_assignment -name DEVICE AGIB023R18A1E1V
+set_global_assignment -name BOARD default
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name ENABLE_ED_CRC_CHECK ON
+set_global_assignment -name MINIMUM_SEU_INTERVAL 0
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8"
+set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
+set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
+set_global_assignment -name USE_CONF_DONE SDM_IO16
+set_global_assignment -name USE_INIT_DONE SDM_IO5
+set_global_assignment -name USE_PWRMGT_ALERT SDM_IO9
+set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7
+set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE"
+set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 01
+set_global_assignment -name GENERATE_PR_RBF_FILE ON
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
+set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
+set_global_assignment -name GENERATE_COMPRESSED_SOF ON
+
+# ==============================================================================
+# Clocks
+# ==============================================================================
+
+set_location_assignment PIN_CU19 -to SYS_CLK_100M
+set_location_assignment PIN_CV20 -to "SYS_CLK_100M(n)"
+set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SYS_CLK_100M
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SYS_CLK_100M
+
+# ==============================================================================
+# LEDs
+# ==============================================================================
+
+set_location_assignment PIN_DA19 -to USER_LED_G
+set_location_assignment PIN_CY20 -to USER_LED_R
+
+set_instance_assignment -name IO_STANDARD "1.2 V" -to USER_LED_G
+set_instance_assignment -name IO_STANDARD "1.2 V" -to USER_LED_R