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devel/_sources/ndk_core/intel/src/comp/network_mod/readme.rst.txt

@@ -0,0 +1,83 @@
+.. _ndk_network_mod:
+
+NETWORK MODULE
+--------------
+
+Typical Configurations
+^^^^^^^^^^^^^^^^^^^^^^
+
+.. list-table::
+    :align: center
+    :header-rows: 1
+
+    * - ETH_CORE_ARCH
+      - E_TILE
+      - F_TILE
+      - CMAC
+    * - ETH_PORT_SPEED
+      - 100, 25, 10
+      - 400, 200, 100, 50, 40, 25, 10
+      - 100
+    * - ETH_PORT_CHAN (for each speed)
+      - 1, 4, 4
+      - 1, 2, 4, 8, 2, 8, 8
+      - 1
+    * - LANES
+      - 4
+      - 8
+      - 4
+    * - MFB Configuration
+      - 1, 8, 8, 8 (512b)
+      - 4, 8, 8, 8 (2048b)
+      - 1, 8, 8, 8 (512b)
+
+Verification Plan
+^^^^^^^^^^^^^^^^^
+
+It is necessary to test all supported Ethernet IP architectures (E-Tile, CMAC,...) and their supported speeds/channels.
+
+.. list-table::
+    :align: center
+    :header-rows: 1
+
+    * - ID
+      - Description
+      - Requirement level
+      - Checked by
+      - Status
+      - Test name
+    * - 1
+      - Dropped packets (overflow, unmasked errors).
+      - Obligatory
+      - Func. cover
+      - TBD
+      - All tests
+    * - 2
+      - Checking the MAC address according to the values written in the configurable TCAM.
+      - Obligatory
+      - Func. cover
+      - TBD
+      - All tests
+    * - 3
+      - Test checking the setting of the minimum and maximum packet length and discarding packets outside the range.
+      - Obligatory
+      - Func. cover
+      - TBD
+      - All tests
+    * - 4
+      - Read out (via MI) and check statistics in RX/TX MAC.
+      - Obligatory
+      - Func. cover
+      - TBD
+      - All tests
+    * - 5
+      - Maximum speed test (output does not brake and input goes full speed), 100% throughput is expected for all packet lengths.
+      - Obligatory
+      - Func. cover
+      - TBD
+      - test::speed
+
+Entity Docs
+^^^^^^^^^^^
+
+.. vhdl:autoentity:: NETWORK_MOD

devel/_sources/ofm_doc/comp/dma/dma_calypte/comp/rx/readme.rst.txt

@@ -12,6 +12,10 @@ in the following figure:
 
 .. vhdl:autoentity:: RX_DMA_CALYPTE
 
+
+Subcomponents
+-------------
+
 .. toctree::
    :maxdepth: 1
    :caption: Subcomponents
@@ -21,3 +25,110 @@ in the following figure:
    comp/hdr_insertor/readme
    comp/hdr_manager/readme
    comp/software_manager/readme
+
+----------------
+UVM Verification
+----------------
+
+.. figure:: img/uvm_ver.jpg
+    :align: center
+    :scale: 60%
+
+
+Verification Plan
+-----------------
+
+TODO:
+
+
+Coverage Mesure
+---------------
+
+There is three test in Multiver script. High percentage of uncovered lines is due to unreacheable states and due to mi comunication with software manager. Mi comunication is tested by hw tests.
+
+.. list-table:: test configuration
+   :widths: 50 50 50 50 50 50
+   :header-rows: 1
+
+   * - conf name
+     - Regions
+     - Max packet size
+     - buffer addres width
+     - input fifo (RX)
+     - channels num
+
+   * - default
+     - 1(~40Gb/s)
+     - 2^16-1
+     - 16-bit
+     - NONE
+     - 2
+
+   * - 32_channel
+     - 1(~40Gb/s)
+     - 2^16-1
+     - 16-bit
+     - NONE
+     - 32
+
+   * - 32_channel
+     - 1(~40Gb/s)
+     - 2^16-1
+     - 16-bit
+     - On input
+     - 2
+
+.. list-table:: coverage
+   :widths: 50 50 50 50
+   :header-rows: 1
+
+   * - conf name
+     - base
+     - full speed
+     - merge
+
+   * - default
+     - 63.1942%
+     - 63.4521%
+     - 64.0038%
+
+   * - 32_channels
+     - 62.6153%
+     - 61.4392%
+     - 62.7494%
+
+   * - opt_fifo_en
+     - 65.3934%
+     - 64.9822%
+     - 65.9905%
+
+Delay is mesure only for full spead test. Which allweys accept output from DUT. Delay represents how many nanoseconds take to go through DMA Calypte.
+
+.. list-table:: delay
+   :widths: 50 50 50 50 50
+   :header-rows: 1
+
+   * - conf name
+     - min
+     - max
+     - average
+     - standard deviation
+
+   * - default
+     - 53ns
+     - 68ns
+     - 57ns
+     - 5ns
+
+   * - 32_channels
+     - 40ns
+     - 1752ns
+     - 56ns
+     - 63ns
+
+   * - opt_fifo_en
+     - 44ns
+     - 428ns
+     - 294ns
+     - 158ns
+

devel/_sources/ofm_doc/comp/dma/dma_calypte/comp/tx/readme.rst.txt

@@ -18,3 +18,151 @@ TX DMA Calypte
 General subcomponents
 ---------------------
 * :ref:`mvb_fifox`
+
+
+----------------
+UVM Verification
+----------------
+
+.. figure:: img/uvm_ver.jpg
+    :align: center
+    :scale: 60%
+
+
+Verification Plan
+-----------------
+
+TODO:
+
+
+Coverage Mesure
+---------------
+
+There is five test in Multiver script.
+
+.. list-table:: test configuration
+   :widths: 50 50 50 50 50 50 50
+   :header-rows: 1
+
+   * - conf name
+     - Regions
+     - Max packet size
+     - buffer addres width (DATA, HDR)
+     - PCIE LEN (MIN, MAX)
+     - channels num
+
+  * - default
+     - 1(~40Gb/s)
+     - 2^11-1
+     - 14-bit, 11-bit
+     - 1.256
+     - 2
+
+  *  - 4_channels
+     - 1(~40Gb/s)
+     - 2^11-1
+     - 14-bit, 11-bit
+     - 1.256
+     - 4
+
+  *  - 8_channels, min_pcie_frames 
+     - 1(~40Gb/s)
+     - 2^11-1
+     - 14-bit, 11-bit
+     - 1.32
+     - 8
+
+  *  - buff_size_small
+     - 1(~40Gb/s)
+     - 2^11-1
+     - 13-bit, 10-bit
+     - 1.256
+     - 2
+
+  *  - buff_size_large 
+     - 1(~40Gb/s)
+     - 2^11-1
+     - 16-bit, 13-bit
+     - 1.256
+     - 2
+
+
+.. list-table:: coverage
+   :widths: 50 50 50 50
+   :header-rows: 1
+
+   * - conf name
+     - base
+     - full speed
+     - merge
+
+   * - default
+     - 75.3494%
+     - 74.9002%
+     - 75.5762%
+
+   * - 4_channels
+     - 76.4729%
+     - 76.4729%
+     - 76.4729%
+
+   * - 8_channels, min_pcie_frames 
+     - 77.6599%
+     - 77.3954%
+     - 77.6599%
+
+   * - buff_size_small
+     - 76.2113%
+     - 75.7632%
+     - 76.4380%
+
+   * - buff_size_large
+     - 75.3069%
+     - 74.8577%
+     - 755337%
+
+
+Delay is mesure only for full spead test. Which allweys accept output from DUT. Delay represents how many nanoseconds take to go through DMA Calypte.
+
+.. list-table:: delay
+   :widths: 50 50 50 50 50
+   :header-rows: 1
+
+   * - conf name
+     - min
+     - max
+     - average
+     - standard deviation
+
+   * - defaulit
+     - 28ns
+     - 500ns
+     - 175ns
+     - 83ns
+
+   * - 4_channels
+     - 28ns
+     - 816ns
+     - 183ns
+     - 97ns
+
+   * - 8_channels, min_pcie_frames 
+     - 24ns
+     - 944ns
+     - 192ns
+     - 111ns
+
+   * - buff_size_small 
+     - 28ns
+     - 500ns
+     - 175ns
+     - 83ns
+
+   * - buff_size_big 
+     - 28ns
+     - 500ns
+     - 175ns
+     - 83ns
+
+
+

devel/_sources/ofm_doc/comp/nic/mac_lite/rx_mac_lite/comp/buffer/uvm/readme.rst.txt

@@ -14,10 +14,10 @@ BUFFER
 Verification Plan
 ^^^^^^^^^^^^^^^^^
 
-========   ================================================                                                                     ===========
-ID          Description                                                                                                         Test
-========   ================================================                                                                     ===========
+========   ============================================================================================================================================================   ===========
+ID          Description                                                                                                                                                   Test
+========   ============================================================================================================================================================   ===========
 1          Send 20000 packet withnout error flag. On output have to be at least 90% of them
-2          Speed test. Send packet 100% - 90% input speed Pactek withnout error flag. Output speed cannot drop bellow 85%. Output DST_RDY have to be set allways to one
-========   ================================================                                                                     ===========
+2          Speed test. Send packet 100% - 90% input speed Pactek withnout error flag. Output speed cannot drop bellow 85%. Output DST_RDY have to be set allways to one   -
+========   ============================================================================================================================================================   ===========
 

devel/_sources/ofm_doc/comp/uvm/mi/readme.rst.txt

@@ -29,7 +29,7 @@ addr     yes      Requested address. Variable is the logic vector width ``ADDR_W
 meta     yes      Metadata. Variable is the logic vector width ``META_WIDTH``.
 be       yes      Byte enable for reading or writing data. Variable is the logic vector width ``DATA_WIDTH/8``.
 wr       yes      Write request. It cannot be asserted when signal rd is asserted.
-dwr      yes      Written data. Variable is the logic vector width ``DATA_WIDTH ``.
+dwr      yes      Written data. Variable is the logic vector width ``DATA_WIDTH``.
 rd       yes      Read request. It cannot be asserted when signal wr is asserted.
 ardy     no       Driver sends a response in this signal if the request has been accepted DUT.
 ======== ======== ================================================
@@ -80,4 +80,4 @@ sequence_master          generate random 10-200 MI transactions
 sequence_master_burst    generate random 10-200 MI transaction to random addresses. When the sequence is randomized, then a burst mode is randomly selected. (NO ARDY and DRDY, ONLY ARDY, ONLY DRDY, ARDY and DRDY). DRDY is generated only when enough requests for reading have been received.
 sequence_master_max      generate random 10-200 MI transaction. Ardy is always asserted. Drdy has one clock cycle delay. This is the implementation's limitation.
 sequence_slave_library   Randomly run MI sequence_slave 100 - 500 sequences on the MI sequencer.
-======================== ================================================
+======================== ================================================

devel/app-minimal.html

@@ -38,7 +38,7 @@
             Minimal NDK Application Docs
           </a>
               <div class="version">
-                Git branch: devel, <br> Git hash: e289da76
+                Git branch: devel, <br> Git hash: 83cc58d9
               </div>
 <div role="search">
   <form id="rtd-search-form" class="wy-form" action="search.html" method="get">