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Various bug fixes #43

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Various bug fixes #43

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c7ea6b5
fix wrong average queue waiting time
Aug 21, 2020
c5eb00a
Fix divide by zero
Aug 23, 2020
aa36326
Cache manager bug fix
Aug 30, 2020
bebe6d6
Check if reading NO_LPA
Aug 30, 2020
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12 changes: 6 additions & 6 deletions src/host/IO_Flow_Base.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -543,15 +543,15 @@ IO_Flow_Base::IO_Flow_Base(const sim_object_id_type &name, uint16_t flow_id, LHA
xmlwriter.Write_attribute_string(attr, val);

attr = "IOPS";
val = std::to_string((double)STAT_generated_request_count / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
val = std::to_string((double)STAT_generated_request_count / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
xmlwriter.Write_attribute_string(attr, val);

attr = "IOPS_Read";
val = std::to_string((double)STAT_generated_read_request_count / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
val = std::to_string((double)STAT_generated_read_request_count / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
xmlwriter.Write_attribute_string(attr, val);

attr = "IOPS_Write";
val = std::to_string((double)STAT_generated_write_request_count / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
val = std::to_string((double)STAT_generated_write_request_count / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
xmlwriter.Write_attribute_string(attr, val);

attr = "Bytes_Transferred";
Expand All @@ -567,15 +567,15 @@ IO_Flow_Base::IO_Flow_Base(const sim_object_id_type &name, uint16_t flow_id, LHA
xmlwriter.Write_attribute_string(attr, val);

attr = "Bandwidth";
val = std::to_string((double)STAT_transferred_bytes_total / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
val = std::to_string((double)STAT_transferred_bytes_total / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
xmlwriter.Write_attribute_string(attr, val);

attr = "Bandwidth_Read";
val = std::to_string((double)STAT_transferred_bytes_read / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
val = std::to_string((double)STAT_transferred_bytes_read / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
xmlwriter.Write_attribute_string(attr, val);

attr = "Bandwidth_Write";
val = std::to_string((double)STAT_transferred_bytes_write / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
val = std::to_string((double)STAT_transferred_bytes_write / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF));
xmlwriter.Write_attribute_string(attr, val);


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2 changes: 1 addition & 1 deletion src/ssd/Data_Cache_Manager_Flash_Advanced.cpp
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Expand Up @@ -85,7 +85,7 @@ namespace SSD_Components
break;
}

delete per_stream_cache;
delete[] per_stream_cache;
delete[] dram_execution_queue;
delete[] waiting_user_requests_queue_for_dram_free_slot;
delete[] bloom_filter;
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4 changes: 4 additions & 0 deletions src/ssd/Data_Cache_Manager_Flash_Simple.cpp
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Expand Up @@ -96,6 +96,8 @@ namespace SSD_Components
if (user_request->Transaction_list.size() > 0) {
static_cast<FTL*>(nvm_firmware)->Address_Mapping_Unit->Translate_lpa_to_ppa_and_dispatch(user_request->Transaction_list);
}

return;
}
default:
PRINT_ERROR("The specified caching mode is not not support in simple cache manager!")
Expand All @@ -113,6 +115,8 @@ namespace SSD_Components
if (user_request->Transaction_list.size() > 0) {
waiting_user_requests_queue_for_dram_free_slot[user_request->Stream_id].push_back(user_request);
}

return;
}
default:
PRINT_ERROR("The specified caching mode is not not support in simple cache manager!")
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4 changes: 3 additions & 1 deletion src/ssd/NVM_PHY_ONFI_NVDDR2.cpp
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Expand Up @@ -326,7 +326,9 @@ namespace SSD_Components {
{
int i = 0;
for (auto &address : command->Address) {
if (address.PlaneID == read_transaction->Address.PlaneID) {
// check if we are not reading a page that has not been written before
if (address.PlaneID == read_transaction->Address.PlaneID &&
command->Meta_data[i].LPA != NO_LPA) {
read_transaction->LPA = command->Meta_data[i].LPA;
}
i++;
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10 changes: 7 additions & 3 deletions src/ssd/Queue_Probe.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -171,16 +171,20 @@ namespace SSD_Components

sim_time_type Queue_Probe::AvgWaitingTime()
{
return (sim_time_type)((double)totalWaitingTime / (double)(nDepartures * 1000));//convert nano-seconds to micro-seconds
if(nDepartures)
return (sim_time_type)((double)totalWaitingTime / (double)(nDepartures * 1000));//convert nano-seconds to micro-seconds
return 0;
}

sim_time_type Queue_Probe::AvgWaitingTimeEpoch()
{
return (sim_time_type)((double)totalWaitingTimeEpoch / (double)(nDeparturesEpoch * 1000));
if(nDeparturesEpoch)
return (sim_time_type)((double)totalWaitingTimeEpoch / (double)(nDeparturesEpoch * 1000));
return 0;
}

sim_time_type Queue_Probe::TotalWaitingTime()
{
return totalWaitingTime;
}
}
}