riscv: Add the modesw.{cap,int} instructions #265
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hmm looks like we need to delete https://github.com/CTSRD-CHERI/qemu/blob/qemu-cheri/.github/lockdown.yml |
This is needed in order to support a RISC-V standards-compatible subset of ISAv9. Code was taken from the CHERI-Alliance repository and adapted for the current dev branch (without support for the older 0.90 version of the standard It should be possible to optimize this instruction more without dropping out of the current TCG translation block, but that would require updating PCC's capmode flag lazily. Co-authored-by: Paul Buxton <[email protected]> Co-authored-by: Martin Kaiser <[email protected]>
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Not sure what is wrong with FreeBSD CI, but hopefully this is simple enough to merge? Needed for CTSRD-CHERI/llvm-project#756 and CTSRD-CHERI/cheribsd#2317 |
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This is needed in order to support a RISC-V standards-compatible subset of ISAv9. Code was taken from the CHERI-Alliance repository and adapted for the current dev branch (without support for the older 0.90 version of the standard).
It should be possible to optimize this instruction more without dropping out of the current TCG translation block, but that would require updating PCC's capmode flag lazily.
Co-authored-by: Paul Buxton [email protected]
Co-authored-by: Martin Kaiser [email protected]