CPU is now cycle-accurate

DreamWest · Dec 3, 2016 · 10b0285 · 10b0285
1 parent 61065f6
commit 10b0285
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Showing 2 changed files with 21 additions and 18 deletions.
diff --git a/src/CPU.cpp b/src/CPU.cpp
@@ -116,9 +116,9 @@ namespace sn
                   << "X:"   << std::setw(2) << +r_X << " "
                   << "Y:"   << std::setw(2) << +r_Y << " "
                   << "P:"   << std::setw(2) << psw << " "
-                  << "SP:"  << std::setw(2) << +r_SP  << std::endl;/*" "
+                  << "SP:"  << std::setw(2) << +r_SP  << /*std::endl;*/" "
                   << "CYC:" << std::setw(3) << std::setfill(' ') << std::dec << ((m_cycles - 1) * 3) % 341
-                  << std::endl;*/
+                  << std::endl;
 
        Byte opcode = m_bus.read(r_PC++);
 
@@ -330,7 +330,8 @@ namespace sn
     {
         if ((opcode & InstructionModeMask) == 0x1)
         {
-            Address location = 0; //Location of the operand, could be in RAM,
+            Address location = 0; //Location of the operand, could be in RAM
+            auto op = static_cast<Operation1>((opcode & OperationMask) >> OperationShift);
             switch (static_cast<AddrMode1>(
                     (opcode & AddrModeMask) >> AddrModeShift))
             {
@@ -355,7 +356,8 @@ namespace sn
                     {
                         Byte zero_addr = m_bus.read(r_PC++);
                         location = m_bus.read(zero_addr & 0xff) | m_bus.read((zero_addr + 1) & 0xff) << 8;
-                        setPageCrossed(location, location + r_Y);
+                        if (op != STA)
+                            setPageCrossed(location, location + r_Y);
                         location += r_Y;
                     }
                     break;
@@ -366,21 +368,22 @@ namespace sn
                 case AbsoluteY:
                     location = readAddress(r_PC);
                     r_PC += 2;
-                    setPageCrossed(location, location + r_Y);
+                    if (op != STA)
+                        setPageCrossed(location, location + r_Y);
                     location += r_Y;
                     break;
                 case AbsoluteX:
                     location = readAddress(r_PC);
                     r_PC += 2;
-                    setPageCrossed(location, location + r_X);
+                    if (op != STA)
+                        setPageCrossed(location, location + r_X);
                     location += r_X;
                     break;
                 default:
                     return false;
             }
 
-            switch (static_cast<Operation1>(
-                                (opcode & OperationMask) >> OperationShift))
+            switch (op)
             {
                 case ORA:
                     r_A |= m_bus.read(location);

diff --git a/src/PPU.cpp b/src/PPU.cpp
@@ -69,12 +69,13 @@ namespace sn
                     {
                         //fetch tile
                         auto addr = 0x2000 | (m_dataAddress & 0x0FFF); //mask off fine y
+                        //auto addr = 0x2000 + x / 8 + (y / 8) * (ScanlineVisibleDots / 8);
                         Byte tile = read(addr);
 
                         //fetch pattern
                         auto x_fine = (m_fineXScroll + x) % 8;
                         //Each pattern occupies 16 bytes, so multiply by 16
-                        addr = (tile * 16) + ((m_dataAddress >> 12) & 0x7); //Add fine y
+                        addr = (tile * 16) + ((m_dataAddress >> 12/*y % 8*/) & 0x7); //Add fine y
                         addr |= m_bgPage << 12; //set whether the pattern is in the high or low page
                         //Get the corresponding bit determined by (8 - x_fine) from the right
                         bgColor = (read(addr) >> (7 ^ x_fine)) & 1; //bit 0 of palette entry
@@ -226,7 +227,7 @@ namespace sn
                     m_cycle = 0;
                 }
 
-                if (m_scanline >= VisibleScanlines)
+                if (m_scanline >= VisibleScanlines - 1)
                     m_pipelineState = PostRender;
 
                 break;
@@ -237,18 +238,18 @@ namespace sn
                     m_cycle = 0;
                     m_pipelineState = VerticalBlank;
                     //Should technically be done at first dot of VBlank, but this is close enough
-                    m_vblank = true;
-                    if (m_generateInterrupt) m_vblankCallback();
+//                     m_vblank = true;
+//                     if (m_generateInterrupt) m_vblankCallback();
 
                 }
 
                 break;
             case VerticalBlank:
-//                 if (m_cycle == 1 && m_scanline == VisibleScanlines + 2)
-//                 {
-//                     m_vblank = true;
-//                     if (m_generateinterrupt) m_vblankcallback();
-//                 }
+                if (m_cycle == 1 && m_scanline == VisibleScanlines + 1)
+                {
+                    m_vblank = true;
+                    if (m_generateInterrupt) m_vblankCallback();
+                }
 
                 if (m_cycle >= ScanlineEndCycle)
                 {
@@ -322,7 +323,6 @@ namespace sn
         //m_dataAddress = 0;
         m_vblank = false;
         m_firstWrite = true;
-        //scroll = 0
         return status;
     }