Bugfix multiple output

.gitignore

@@ -1,6 +1,5 @@
 .pioenvs
-*.v
-*.pcf
+*.out
 *.asc
 *.bin
 *.blif

examples/example.ice

@@ -1 +1 @@
-{"nodes":[],"connections":[]}
+{"nodes":[{"name":"","type":"driver0","value":0,"inline":"assign o0 = 1'b0;","id":11,"x":235,"y":151,"width":50,"outputConnectors":[{"name":"\"0\""}]},{"name":"","type":"output","value":"95","id":12,"x":403,"y":111,"width":60,"inputConnectors":[{"name":"95"}]},{"name":"","type":"output","value":"96","id":13,"x":396,"y":217,"width":60,"inputConnectors":[{"name":"96"}]}],"connections":[{"source":{"nodeID":11,"connectorIndex":0},"dest":{"nodeID":12,"connectorIndex":0}},{"source":{"nodeID":11,"connectorIndex":0},"dest":{"nodeID":13,"connectorIndex":0}}]}

gui/build.py

@@ -153,14 +153,19 @@ def generate_verilog_main(name, nodes, connections):
         if node['type'] != 'input' and node['type'] != 'output':
             inline += node['type'] + 'x '
             inline += node['type'] + str(node['id']) + ' (\n'
+            io = []
             params = []
             for index, connection in enumerate(connections):
                 if node['id'] == connection['source']['nodeID']:
                     param = 'o' + str(connection['source']['connectorIndex'])
-                    params += ['    .{0}(w{1})'.format(param, index)]
+                    if param not in io:
+                        io += [param]
+                        params += ['    .{0}(w{1})'.format(param, index)]
                 if node['id'] == connection['dest']['nodeID']:
                     param = 'i' + str(connection['dest']['connectorIndex'])
-                    params += ['    .{0}(w{1})'.format(param, index)]
+                    if param not in io:
+                        io += [param]
+                        params += ['    .{0}(w{1})'.format(param, index)]
             inline += ',\n'.join(params) + '\n'
             inline += ');\n'
 

src/main.pcf

@@ -0,0 +1,2 @@
+set_io output12 95
+set_io output13 96

src/main.v

@@ -1,4 +1,16 @@
 // Generated verilog
 
-module main();
+module driver0x(output o0);
+assign o0 = 1'b0;
+endmodule
+
+module main(output output12, output13);
+wire w0;
+wire w1;
+assign output12 = w0;
+assign output13 = w1;
+assign w0 = w1;
+driver0x driver011 (
+    .o0(w0)
+);
 endmodule