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Rewrite fuel_asm::impl_instructions! to a proc macro #804

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3 changes: 3 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

### Changed
- [#804](https://github.com/FuelLabs/fuel-vm/pull/804): Refactor `impl_instructions!` macro. No externally visible changes.

## [Version 0.56.0]

### Added
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1 change: 1 addition & 0 deletions fuel-asm/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ description = "Atomic types of the FuelVM."
[dependencies]
arbitrary = { version = "1.1", features = ["derive"], optional = true }
bitflags = { workspace = true }
fuel-derive = { workspace = true }
fuel-types = { workspace = true }
serde = { version = "1.0", default-features = false, features = ["derive"], optional = true }
strum = { version = "0.24", default-features = false, features = ["derive"] }
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51 changes: 20 additions & 31 deletions fuel-asm/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,15 +18,10 @@
extern crate alloc;

mod args;
mod panic_instruction;
// This is `pub` to make documentation for the private `impl_instructions!` macro more
// accessible.
#[macro_use]
pub mod macros;
mod macros;
pub mod op;
mod pack;
mod panic_instruction;
mod panic_reason;
mod unpack;

#[cfg(test)]
mod encoding_tests;
Expand Down Expand Up @@ -93,6 +88,7 @@ bitflags::bitflags! {
const WRAPPING = 0x02;
}
}

/// Type is convertible to a [`RegId`]
pub trait CheckRegId {
/// Convert to a [`RegId`], or panic
Expand All @@ -114,7 +110,7 @@ impl CheckRegId for u8 {
// Defines the `Instruction` and `Opcode` types, along with an `op` module declaring a
// unique type for each opcode's instruction variant. For a detailed explanation of how
// this works, see the `fuel_asm::macros` module level documentation.
impl_instructions! {
fuel_derive::impl_instructions! {
"Adds two registers."
0x10 ADD add [dst: RegId lhs: RegId rhs: RegId]
"Bitwise ANDs two registers."
Expand Down Expand Up @@ -608,6 +604,10 @@ impl Imm06 {
pub const fn to_u8(self) -> u8 {
self.0
}

pub(crate) fn to_smallest_int(self) -> u8 {
self.to_u8()
}
}

impl Imm12 {
Expand All @@ -633,6 +633,10 @@ impl Imm12 {
pub const fn to_u16(self) -> u16 {
self.0
}

pub(crate) fn to_smallest_int(self) -> u16 {
self.to_u16()
}
}

impl Imm18 {
Expand All @@ -658,6 +662,10 @@ impl Imm18 {
pub const fn to_u32(self) -> u32 {
self.0
}

pub(crate) fn to_smallest_int(self) -> u32 {
self.to_u32()
}
}

impl Imm24 {
Expand All @@ -683,6 +691,10 @@ impl Imm24 {
pub const fn to_u32(self) -> u32 {
self.0
}

pub(crate) fn to_smallest_int(self) -> u32 {
self.to_u32()
}
}

impl Opcode {
Expand Down Expand Up @@ -934,29 +946,6 @@ where
us.into_iter().map(Instruction::try_from)
}

// Short-hand, `panic!`ing constructors for the short-hand instruction construtors (e.g
// op::add).

fn check_imm06(u: u8) -> Imm06 {
Imm06::new_checked(u)
.unwrap_or_else(|| panic!("Value `{u}` out of range for 6-bit immediate"))
}

fn check_imm12(u: u16) -> Imm12 {
Imm12::new_checked(u)
.unwrap_or_else(|| panic!("Value `{u}` out of range for 12-bit immediate"))
}

fn check_imm18(u: u32) -> Imm18 {
Imm18::new_checked(u)
.unwrap_or_else(|| panic!("Value `{u}` out of range for 18-bit immediate"))
}

fn check_imm24(u: u32) -> Imm24 {
Imm24::new_checked(u)
.unwrap_or_else(|| panic!("Value `{u}` out of range for 24-bit immediate"))
}

// --------------------------------------------------------

// The size of the instruction isn't larger than necessary.
Expand Down
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