🎯
Focusing
I'm a research engineer fighting in network and system area, but have a heart of geek.
-
Huawei
- guanyu.li
Pinned Loading
-
-
FiveStage-MIPS-CPU
FiveStage-MIPS-CPU PublicComplete a 5-stage MIPS CPU with multi-level interrupts and dynamic branch prediction on logisim and verilog
Verilog 3
-
-
SingleCycle-MIPS-CPU
SingleCycle-MIPS-CPU PublicComplete a single-cycle MIPS CPU on logisim
Assembly
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.