Change frequency to 48 MHz

constraint.sdc

@@ -24,13 +24,13 @@ set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $io_clk_input_ports
 set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $io_clk_output_ports
 
 set_ideal_network [get_pins u_pad_io_clk/p2c]
-create_clock [get_pins u_pad_io_clk/p2c] -name p_io_clk -period 48 -waveform {0 24}
+create_clock [get_pins u_pad_io_clk/p2c] -name p_io_clk -period 20.8333333
 set_clock_uncertainty 0.15 [get_clocks p_io_clk]
 set_clock_transition 0.25 [get_clocks p_io_clk]
 
-set_input_delay  8 -clock p_io_clk [get_ports { p_io_clk }]
-set_input_delay  8 -clock p_io_clk $io_clk_input_ports
-set_output_delay 8 -clock p_io_clk $io_clk_output_ports
+set_input_delay  2 -clock p_io_clk [get_ports { p_io_clk }]
+set_input_delay  2 -clock p_io_clk $io_clk_input_ports
+set_output_delay 2 -clock p_io_clk $io_clk_output_ports
 
 set_load -pin_load 5 [all_inputs]
 set_load -pin_load 5 [all_outputs]

src/AesTb.v

@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.10.1    git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
 // Component : AesTb
-// Git hash  : 40b01e91e00e653d35a730e75064f966357fa5ed
+// Git hash  : 7d71b394980eea21c4797418cfad392826f876d0
 
 `timescale 1ns/1ps
 
@@ -123,7 +123,7 @@ module AesTb (
     .io_reset  (io_reset                   )  //i
   );
   assign aesIsDone = 1'b0;
-  assign uartCtrl_1_io_config_clockDivider = 20'h0000a;
+  assign uartCtrl_1_io_config_clockDivider = 20'h00033;
   assign uartCtrl_1_io_config_frame_dataLength = 3'b111;
   assign uartCtrl_1_io_config_frame_parity = UartParityType_NONE;
   assign uartCtrl_1_io_config_frame_stop = UartStopType_ONE;