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VAESENC
VAESENC — Perform One Round of an AES Encryption Flow
| Opcode/ Instruction | Op/ En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
| VEX.256.66.0F38.WIG DC /r VAESENC ymm1, ymm2, ymm3/m256 | A | V/V | VAES | Perform one round of an AES encryption flow, operating on a 128-bit data (state) from ymm2 with a 128-bit round key from the ymm3/m256; store the result in ymm1. |
| EVEX.128.66.0F38.WIG DC /r VAESENC xmm1, xmm2, xmm3/m128 | B | V/V | AVX512VL VAES | Perform one round of an AES encryption flow, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from the xmm3/m128; store the result in xmm1. |
| EVEX.256.66.0F38.WIG DC /r VAESENC ymm1, ymm2, ymm3/m256 | B | V/V | AVX512VL VAES | Perform one round of an AES encryption flow, operating on a 128-bit data (state) from ymm2 with a 128-bit round key from the ymm3/m256; store the result in ymm1. |
| EVEX.512.66.0F38.WIG DC /r VAESENC zmm1, zmm2, zmm3/m512 | B | V/V | AVX512F VAES | Perform one round of an AES encryption flow, operating on a 128-bit data (state) from zmm2 with a 128-bit round key from the zmm3/m512; store the result in zmm1. |
| Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| A | NA | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | NA |
| B | Full Mem | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | NA |
This instruction performs a single round of an AES encryption flow using a round key from the second source operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination operand.
Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENCCLAST instruction.
VEX and EVEX encoded versions of the instruction allows 3-operand (non-destructive) operation. The legacy encoded versions of the instruction require that the first source operand and the destination operand are the same and must be an XMM register.
The EVEX encoded form of this instruction does not support memory fault suppression.
STATE ← SRC1
RoundKey ← SRC2
STATE ← ShiftRows( STATE )
STATE ← SubBytes( STATE )
STATE ← MixColumns( STATE )
DEST[127:0] ← STATE XOR RoundKey
DEST[MAXVL-1:128] (Unmodified)(KL,VL) = (1,128), (2,256)
FOR I ← 0 to KL-1:
STATE ← SRC1.xmm[i]
RoundKey ← SRC2.xmm[i]
STATE ← ShiftRows( STATE )
STATE ← SubBytes( STATE )
STATE ← MixColumns( STATE )
DEST.xmm[i] ← STATE XOR RoundKey
DEST[MAXVL-1:VL] ← 0(KL,VL) = (1,128), (2,256), (4,512)
FOR i ← 0 to KL-1:
STATE ← SRC1.xmm[i] // xmm[i] is the i’th xmm word in the SIMD register
RoundKey ← SRC2.xmm[i]
STATE ← ShiftRows( STATE )
STATE ← SubBytes( STATE )
STATE ← MixColumns( STATE )
DEST.xmm[i] ← STATE XOR RoundKey
DEST[MAXVL-1:VL] ← 0VAESENC __m256i _mm256_aesenc_epi128(__m256i, __m256i);
VAESENC __m512i _mm512_aesenc_epi128(__m512i, __m512i);None.
VEX-encoded: Exceptions Type 4. EVEX-encoded: See Exceptions Type E4NF.
Source: Intel® Architecture Instruction Set Extensions and Future Features Programming Reference (May 2019)
Generated: 28-5-2019