RISC-V: Fix set_register for vector registers

Signed-Off-By: Patrick O'Neill <[email protected]>
IBM · Jun 27, 2024 · 671ccd6 · 671ccd6
1 parent 1b550b6
commit 671ccd6
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Showing 2 changed files with 5 additions and 19 deletions.
diff --git a/targets/riscv/isa/riscv-common/isa.py b/targets/riscv/isa/riscv-common/isa.py
@@ -240,40 +240,26 @@ def set_register(
 
             else:
                 # Load the value into the vector register 1 chunk at a time.
-                # TODO: Fix this.
-                # Currently each chunk will overwrite the existing chunks.
 
                 chunks = [
                     (value >> 1024 - (64 * i)) & 0xFFFFFFFFFFFFFFFF
                     for i in range(1, 17)
                 ]
 
                 for chunk in chunks:
-                    # Set register to shift amount
+                    # Set int register to chunk
                     instrs.extend(
                         self.set_register(
-                            self._scratch_registers[0], 64, context)
+                            self._scratch_registers[0], chunk, context)
                     )
 
-                    # Shift existing vector register value
-                    shiftleft = self.new_instruction("VSLL.VX_V0")
+                    # Shift existing vector register value and insert chunk
+                    shiftleft = self.new_instruction("VSLIDE1UP.VX_V0")
                     shiftleft.set_operands(
                         [register, register, self._scratch_registers[0]]
                     )
                     instrs.append(shiftleft)
 
-                    # Set int register to chunk
-                    instrs.extend(
-                        self.set_register(
-                            self._scratch_registers[0], chunk, context)
-                    )
-
-                    # Add chunk to the shifted register
-                    vadd = self.new_instruction("VADD.VX_V0")
-                    vadd.set_operands(
-                        [register, register, self._scratch_registers[0]])
-                    instrs.append(vadd)
-
             LOG.debug(f"Register: {register.name} set to value {value}")
         elif register.type.name == "LMUL" and value in [lmul << 9 | sew & 127 for lmul in [1, 2, 4, 8] for sew in [8, 16, 32, 64]]:
             sew = value & 127

diff --git a/targets/riscv/policies/seq.py b/targets/riscv/policies/seq.py
@@ -105,7 +105,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(
-            value=RNDINT(), lmul=lmul, sew=sew
+            value=rand.randint(0, (2**1024)), lmul=lmul, sew=sew
         )
     )