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Update RISCV ISA by parsing binutils#44

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patrick-rivos wants to merge 4 commits intoIBM:masterIBM/microprobe:masterfrom patrick-rivos:update-riscv-isapatrick-rivos/microprobe:update-riscv-isaCopy head branch name to clipboard

+6,591-41

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Commits on Nov 16, 2024

• Add RISC-V binutils format parser to devtools

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• Add preliminary RISC-V vector support (Assembly only)

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• RISC-V: Expose sew and lmul to mp_seq.py command line

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• RISC-V: Remove insn aliases

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