feat(widths): Add correct widths to if_gen interfaces.

Add `widths` dictionary to generate interfaces with widths based on CACHE parameters.
IObundle · Oct 19, 2023 · ec66dbe · ec66dbe
1 parent 754b86c
commit ec66dbe
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Showing 2 changed files with 19 additions and 1 deletion.
diff --git a/iob_cache.py b/iob_cache.py
@@ -288,6 +288,12 @@ def _init_attributes(cls):
                 "wire_prefix": "",
                 "descr": "AXI4 interface",
                 "ports": [],
+                "widths": {
+                    "ID_W": "AXI_ID_W",
+                    "ADDR_W": "AXI_ADDR_W",
+                    "DATA_W": "AXI_DATA_W",
+                    "LEN_W": "AXI_LEN_W",
+                },
             },
             {
                 "name": "axi_write",
@@ -296,6 +302,12 @@ def _init_attributes(cls):
                 "wire_prefix": "",
                 "descr": "AXI4 write interface",
                 "ports": [],
+                "widths": {
+                    "ID_W": "AXI_ID_W",
+                    "ADDR_W": "AXI_ADDR_W",
+                    "DATA_W": "AXI_DATA_W",
+                    "LEN_W": "AXI_LEN_W",
+                },
             },
             {
                 "name": "axi_read",
@@ -304,6 +316,12 @@ def _init_attributes(cls):
                 "wire_prefix": "",
                 "descr": "AXI4 read interface",
                 "ports": [],
+                "widths": {
+                    "ID_W": "AXI_ID_W",
+                    "ADDR_W": "AXI_ADDR_W",
+                    "DATA_W": "AXI_DATA_W",
+                    "LEN_W": "AXI_LEN_W",
+                },
             },
             {
                 "name": "fe",

diff --git a/submodules/LIB b/submodules/LIB