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feat(swregs): use fixed swregs #286

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merged 2 commits into from
Oct 20, 2023
Merged

feat(swregs): use fixed swregs #286

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fd7873a
feat(swregs): use fixed swregs
P-Miranda Oct 20, 2023
43aaef5
fix: add missing portmap
P-Miranda Oct 20, 2023
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18 changes: 10 additions & 8 deletions iob_cache.py
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Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,7 @@ def _create_submodules_list(cls):
super()._create_submodules_list(
[
{"interface": "iob_s_port"},
{"interface": "iob_s_portmap"},
{"interface": "axi_m_port"},
{"interface": "axi_m_m_portmap"},
{"interface": "axi_m_write_port"},
Expand Down Expand Up @@ -412,6 +413,7 @@ def _setup_ios(cls):

@classmethod
def _setup_regs(cls):
cls.autoaddr = False
cls.regs += [
{
"name": "cache",
Expand All @@ -422,7 +424,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 1,
"rst_val": 0,
"addr": -1,
"addr": 0,
"log2n_items": 0,
"autologic": False,
"descr": "Write-through buffer empty (1) or non-empty (0).",
Expand All @@ -432,7 +434,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 1,
"rst_val": 0,
"addr": -1,
"addr": 1,
"log2n_items": 0,
"autologic": False,
"descr": "Write-through buffer full (1) or non-full (0).",
Expand All @@ -442,7 +444,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 32,
"rst_val": 0,
"addr": -1,
"addr": 4,
"log2n_items": 0,
"autologic": False,
"descr": "Read and write hit counter.",
Expand All @@ -452,7 +454,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 32,
"rst_val": 0,
"addr": -1,
"addr": 8,
"log2n_items": 0,
"autologic": False,
"descr": "Read and write miss counter.",
Expand All @@ -462,7 +464,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 32,
"rst_val": 0,
"addr": -1,
"addr": 12,
"log2n_items": 0,
"autologic": False,
"descr": "Read hit counter.",
Expand All @@ -472,7 +474,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 32,
"rst_val": 0,
"addr": -1,
"addr": 16,
"log2n_items": 0,
"autologic": False,
"descr": "Read miss counter.",
Expand All @@ -482,7 +484,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 32,
"rst_val": 0,
"addr": -1,
"addr": 20,
"log2n_items": 0,
"autologic": False,
"descr": "Write hit counter.",
Expand All @@ -492,7 +494,7 @@ def _setup_regs(cls):
"type": "R",
"n_bits": 32,
"rst_val": 0,
"addr": -1,
"addr": 24,
"log2n_items": 0,
"autologic": False,
"descr": "Write miss counter.",
Expand Down
2 changes: 1 addition & 1 deletion submodules/LIB
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Submodule LIB updated 11 files
+1 −6 hardware/fpga/quartus/build.tcl
+8 −6 hardware/fpga/quartus/timing.tcl
+3 −0 hardware/modules/iob_interface/README.md
+10 −0 hardware/modules/iob_interface/iob_if_read.drom
+ − hardware/modules/iob_interface/iob_if_read.png
+76 −0 hardware/modules/iob_pulse_gen/hardware/simulation/src/iob_pulse_gen_tb.v
+17 −2 hardware/modules/iob_pulse_gen/hardware/src/iob_pulse_gen.v
+1 −1 hardware/syn/Makefile
+4 −2 scripts/iob_module.py
+33 −9 scripts/mkregs.py
+72 −0 scripts/netlist_proc.py