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Merge branch 'master' of github.com:arturum1/iob-soc-opencryptolinux
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@arturum1
arturum1 committed Jun 18, 2024
2 parents 8eeed8d + 07a9982 commit 76b284b
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32 changes: 16 additions & 16 deletions .github/workflows/ci.yml
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Expand Up @@ -66,22 +66,22 @@ jobs:
- name: icarus test
run: nix-shell --run "make -C ../iob_soc_o* sim-run"

# verilator-baremetal:
# runs-on: self-hosted
# timeout-minutes: 90
# # run even if previous job failed
# if: ${{ !cancelled() }}
#
# steps:
# - uses: actions/checkout@v4
# with:
# submodules: 'recursive'
# - name: clean
# run: nix-shell --run "make clean"
# - name: setup no_init_mem ext_mem
# run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0"
# - name: verilator test
# run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"
verilator-baremetal:
runs-on: self-hosted
timeout-minutes: 90
# run even if previous job failed
if: ${{ !cancelled() }}

steps:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: clean
run: nix-shell --run "make clean"
- name: setup no_init_mem ext_mem
run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0"
- name: verilator test
run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator"


cyclonev:
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6 changes: 6 additions & 0 deletions hardware/simulation/sim_build.mk
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Expand Up @@ -10,6 +10,12 @@ VTOP:=iob_soc_opencryptolinux_tb
# SOURCES
ifeq ($(SIMULATOR),verilator)

VSRC+=./src/iob_tasks.cpp

ifeq ($(USE_ETHERNET),1)
VSRC+=./src/iob_eth_swreg_emb_verilator.c ./src/iob_eth_driver_tb.cpp
endif

# verilator top module
VTOP:=iob_soc_opencryptolinux_sim_wrapper

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273 changes: 131 additions & 142 deletions hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v
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Expand Up @@ -13,101 +13,91 @@
`endif

module iob_soc_opencryptolinux_sim_wrapper (
`include "clk_rst_s_port.vs"
output trap_o,
`include "clk_rst_s_port.vs"
output trap_o,

`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET
// Ethernet for testbench
input ethernet_valid_i,
input [`IOB_ETH_SWREG_ADDR_W-1:0] ethernet_addr_i,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_wdata_i,
input [3:0] ethernet_wstrb_i,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_rdata_o,
output ethernet_ready_o,
output ethernet_rvalid_o,
// Ethernet for testbench
input ethernet_valid_i,
input [ `IOB_ETH_SWREG_ADDR_W-1:0] ethernet_addr_i,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_wdata_i,
input [ 3:0] ethernet_wstrb_i,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_rdata_o,
output ethernet_ready_o,
output ethernet_rvalid_o,
`endif

// UART for testbench
input uart_valid_i,
input [`IOB_UART_SWREG_ADDR_W-1:0] uart_addr_i,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_wdata_i,
input [3:0] uart_wstrb_i,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_rdata_o,
output uart_ready_o,
output uart_rvalid_o
// UART for testbench
input uart_valid_i,
input [ `IOB_UART_SWREG_ADDR_W-1:0] uart_addr_i,
input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_wdata_i,
input [ 3:0] uart_wstrb_i,
output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_rdata_o,
output uart_ready_o,
output uart_rvalid_o
);

localparam AXI_ID_W = 4;
localparam AXI_LEN_W = 8;
localparam AXI_ADDR_W = `DDR_ADDR_W;
localparam AXI_DATA_W = `DDR_DATA_W;
localparam AXI_ID_W = 4;
localparam AXI_LEN_W = 8;
localparam AXI_ADDR_W = `DDR_ADDR_W;
localparam AXI_DATA_W = `DDR_DATA_W;

`include "iob_soc_opencryptolinux_wrapper_pwires.vs"
`include "iob_soc_opencryptolinux_wrapper_pwires.vs"

/////////////////////////////////////////////
// TEST PROCEDURE
//
initial begin
`ifdef VCD
$dumpfile("uut.vcd");
$dumpvars();
`endif
end

//
// INSTANTIATE COMPONENTS
//
//
// INSTANTIATE COMPONENTS
//

//
// IOb-SoC-OpenCryptoLinux (may also include Unit Under Test)
//
iob_soc_opencryptolinux #(
//
// IOb-SoC-OpenCryptoLinux (may also include Unit Under Test)
//
iob_soc_opencryptolinux #(
.AXI_ID_W (AXI_ID_W),
.AXI_LEN_W (AXI_LEN_W),
.AXI_ADDR_W(AXI_ADDR_W),
.AXI_DATA_W(AXI_DATA_W)
) soc0 (
) soc0 (
`include "iob_soc_opencryptolinux_pportmaps.vs"
.clk_i (clk_i),
.cke_i (1'b1),
.arst_i(arst_i),
.trap_o(trap_o)
);
);


// interconnect clk and arst
wire clk_interconnect;
wire arst_interconnect;
assign clk_interconnect = clk_i;
assign arst_interconnect = arst_i;
// interconnect clk and arst
wire clk_interconnect;
wire arst_interconnect;
assign clk_interconnect = clk_i;
assign arst_interconnect = arst_i;

`include "iob_soc_opencryptolinux_interconnect.vs"
`include "iob_soc_opencryptolinux_interconnect.vs"

//instantiate the axi memory
//IOb-SoC-OpenCryptoLinux and SUT access the same memory.
axi_ram #(
//instantiate the axi memory
//IOb-SoC-OpenCryptoLinux and SUT access the same memory.
axi_ram #(
`ifdef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM
.FILE ("init_ddr_contents"), //This file contains firmware for both systems
`endif
.ID_WIDTH (AXI_ID_W),
.DATA_WIDTH(AXI_DATA_W),
.ADDR_WIDTH(AXI_ADDR_W)
) ddr_model_mem (
) ddr_model_mem (
`include "iob_memory_axi_s_portmap.vs"

.clk_i(clk_i),
.rst_i(arst_i)
);
);

//Manually added testbench uart core. RS232 pins attached to the same pins
//of the iob_soc UART0 instance to communicate with it
// The interface of iob_soc UART0 is assumed to be the first portmapped interface (UART_*)
iob_uart uart_tb (
//Manually added testbench uart core. RS232 pins attached to the same pins
//of the iob_soc UART0 instance to communicate with it
// The interface of iob_soc UART0 is assumed to be the first portmapped interface (UART_*)
iob_uart uart_tb (
.clk_i (clk_i),
.cke_i (1'b1),
.arst_i(arst_i),

.iob_valid_i(uart_valid_i),
.iob_valid_i (uart_valid_i),
.iob_addr_i (uart_addr_i),
.iob_wdata_i (uart_wdata_i),
.iob_wstrb_i (uart_wstrb_i),
Expand All @@ -119,94 +109,93 @@ module iob_soc_opencryptolinux_sim_wrapper (
.rxd_i(uart_txd_o),
.rts_o(uart_cts_i),
.cts_i(uart_rts_o)
);
);

//Ethernet
//Ethernet
`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET
//ethernet clock: 4x slower than system clock
reg [1:0] eth_cnt = 2'b0;
reg eth_clk;

always @(posedge clk_i) begin
eth_cnt <= eth_cnt + 1'b1;
eth_clk <= eth_cnt[1];
end

// Ethernet Interface signals
assign ETH0_MRxClk = eth_clk;
assign ETH0_MTxClk = eth_clk;

//Manually added testbench ethernet core. MII pins attached to the same pins
//of the iob_soc ETH0 instance to communicate with it
// The interface of iob_soc ETH0 is assumed to be the first portmapped interface (ETH_*)
iob_eth
#(
.AXI_ID_W(AXI_ID_W),
//ethernet clock: 4x slower than system clock
reg [1:0] eth_cnt = 2'b0;
reg eth_clk;

always @(posedge clk_i) begin
eth_cnt <= eth_cnt + 1'b1;
eth_clk <= eth_cnt[1];
end

// Ethernet Interface signals
assign ETH0_MRxClk = eth_clk;
assign ETH0_MTxClk = eth_clk;

//Manually added testbench ethernet core. MII pins attached to the same pins
//of the iob_soc ETH0 instance to communicate with it
// The interface of iob_soc ETH0 is assumed to be the first portmapped interface (ETH_*)
iob_eth #(
.AXI_ID_W (AXI_ID_W),
.AXI_ADDR_W(AXI_ADDR_W),
.AXI_DATA_W(AXI_DATA_W),
.AXI_LEN_W(AXI_LEN_W)
) eth_tb (
.inta_o(),
.MTxClk(eth_clk),
.MTxD(ETH0_MRxD),
.MTxEn(ETH0_MRxDv),
.MTxErr(ETH0_MRxErr),
.MRxClk(eth_clk),
.MRxDv(ETH0_MTxEn),
.MRxD(ETH0_MTxD),
.MRxErr(ETH0_MTxErr),
.MColl(1'b0),
.MCrS(1'b0),
.MDC(),
.MDIO(),
.iob_valid_i(ethernet_valid_i),
.iob_addr_i (ethernet_addr_i),
.iob_wdata_i (ethernet_wdata_i),
.iob_wstrb_i (ethernet_wstrb_i),
.iob_rvalid_o(ethernet_rvalid_o),
.iob_rdata_o (ethernet_rdata_o),
.iob_ready_o (ethernet_ready_o),
.axi_awid_o (),
.axi_awaddr_o (),
.axi_awlen_o (),
.axi_awsize_o (),
.axi_awburst_o (),
.axi_awlock_o (),
.axi_awcache_o (),
.axi_awprot_o (),
.axi_awqos_o (),
.axi_awvalid_o (),
.axi_awready_i (1'b0),
.axi_wdata_o (),
.axi_wstrb_o (),
.axi_wlast_o (),
.axi_wvalid_o (),
.axi_wready_i (1'b0),
.axi_bid_i ({AXI_ID_W{1'b0}}),
.axi_bresp_i (2'b0),
.axi_bvalid_i (1'b0),
.axi_bready_o (),
.axi_arid_o (),
.axi_araddr_o (),
.axi_arlen_o (),
.axi_arsize_o (),
.axi_arburst_o (),
.axi_arlock_o (),
.axi_arcache_o (),
.axi_arprot_o (),
.axi_arqos_o (),
.axi_arvalid_o (),
.axi_arready_i (1'b0),
.axi_rid_i ({AXI_ID_W{1'b0}}),
.axi_rdata_i ({AXI_DATA_W{1'b0}}),
.axi_rresp_i (2'b0),
.axi_rlast_i (1'b0),
.axi_rvalid_i (1'b0),
.axi_rready_o (),
.clk_i(clk_i),
.arst_i(arst_i),
.cke_i(1'b1)
);
.AXI_LEN_W (AXI_LEN_W)
) eth_tb (
.inta_o (),
.MTxClk (eth_clk),
.MTxD (ETH0_MRxD),
.MTxEn (ETH0_MRxDv),
.MTxErr (ETH0_MRxErr),
.MRxClk (eth_clk),
.MRxDv (ETH0_MTxEn),
.MRxD (ETH0_MTxD),
.MRxErr (ETH0_MTxErr),
.MColl (1'b0),
.MCrS (1'b0),
.MDC (),
.MDIO (),
.iob_valid_i (ethernet_valid_i),
.iob_addr_i (ethernet_addr_i),
.iob_wdata_i (ethernet_wdata_i),
.iob_wstrb_i (ethernet_wstrb_i),
.iob_rvalid_o (ethernet_rvalid_o),
.iob_rdata_o (ethernet_rdata_o),
.iob_ready_o (ethernet_ready_o),
.axi_awid_o (),
.axi_awaddr_o (),
.axi_awlen_o (),
.axi_awsize_o (),
.axi_awburst_o(),
.axi_awlock_o (),
.axi_awcache_o(),
.axi_awprot_o (),
.axi_awqos_o (),
.axi_awvalid_o(),
.axi_awready_i(1'b0),
.axi_wdata_o (),
.axi_wstrb_o (),
.axi_wlast_o (),
.axi_wvalid_o (),
.axi_wready_i (1'b0),
.axi_bid_i ({AXI_ID_W{1'b0}}),
.axi_bresp_i (2'b0),
.axi_bvalid_i (1'b0),
.axi_bready_o (),
.axi_arid_o (),
.axi_araddr_o (),
.axi_arlen_o (),
.axi_arsize_o (),
.axi_arburst_o(),
.axi_arlock_o (),
.axi_arcache_o(),
.axi_arprot_o (),
.axi_arqos_o (),
.axi_arvalid_o(),
.axi_arready_i(1'b0),
.axi_rid_i ({AXI_ID_W{1'b0}}),
.axi_rdata_i ({AXI_DATA_W{1'b0}}),
.axi_rresp_i (2'b0),
.axi_rlast_i (1'b0),
.axi_rvalid_i (1'b0),
.axi_rready_o (),
.clk_i (clk_i),
.arst_i (arst_i),
.cke_i (1'b1)
);
`endif

`ifndef VERILATOR
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1 change: 1 addition & 0 deletions software/src/iob_soc_opencryptolinux_boot.c
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Expand Up @@ -24,6 +24,7 @@
// NOTE: These functions are not compatible with malloc() and free().
// These are specifically made for use with the current iob-eth.c drivers.
// (These assume that there is only one block allocated at a time)
// It allocates a block with required size at the end of the external memory region.
static void *mem_alloc(size_t size) {
return (void *)(EXT_MEM | (1 << IOB_SOC_OPENCRYPTOLINUX_MEM_ADDR_W)) - size;
}
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2 changes: 1 addition & 1 deletion submodules/ETHERNET
Submodule ETHERNET updated 14 files
+4 −3 Makefile
+6 −1 README.md
+12 −0 hardware/simulation/sim_build.mk
+64 −0 hardware/simulation/src/iob_eth_defines_verilator.h
+135 −0 hardware/simulation/src/iob_eth_driver_tb.cpp
+7 −0 hardware/simulation/src/iob_eth_driver_tb.h
+0 −2 hardware/simulation/src/iob_eth_driver_tb.v
+12 −1 hardware/simulation/src/iob_eth_mem_wrapper.v
+289 −0 hardware/simulation/src/iob_eth_tb.cpp
+5 −5 hardware/src/iob_eth.v
+9 −6 iob_eth.py
+5 −140 software/src/iob-eth-defines.h
+1 −1 software/src/iob-eth.c
+144 −0 software/src/iob_eth_macros.h
2 changes: 1 addition & 1 deletion submodules/IOBSOC
Submodule IOBSOC updated 13 files
+6 −0 hardware/simulation/sim_build.mk
+132 −143 hardware/simulation/src/iob_soc_sim_wrapper.v
+84 −89 hardware/simulation/src/iob_soc_tb.cpp
+10 −0 hardware/simulation/src/iob_soc_tb.v
+1 −0 scripts/iob_soc_utils.py
+1 −1 submodules/LIB/document/tsrc/config.tex
+120 −0 submodules/LIB/hardware/modules/iob_tasks/iob_tasks.cpp
+36 −0 submodules/LIB/hardware/modules/iob_tasks/iob_tasks.h
+8 −8 submodules/LIB/hardware/modules/iob_tasks/iob_tasks.py
+8 −1 submodules/LIB/hardware/simulation/verilator.mk
+1 −1 submodules/LIB/scripts/config_gen.py
+114 −0 submodules/LIB/scripts/csr_gen.py
+1 −1 submodules/LIB/scripts/iob_module.py

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