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Fix on missing folder #3

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merged 2 commits into from
Jul 30, 2024
Merged

Fix on missing folder #3

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dc1d6ee
Fix on missing folder
zettasticks Jul 30, 2024
39c4426
Updated actions
zettasticks Jul 30, 2024
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12 changes: 6 additions & 6 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ jobs:
- uses: actions/checkout@v3
with:
submodules: 'recursive'
# - name: test-clean
# run: make test-clean
- name: test-clean
run: make clean
- name: test-pc-emul
run: make pc-emul-run

Expand All @@ -45,8 +45,8 @@ jobs:
- uses: actions/checkout@v3
with:
submodules: 'recursive'
#- name: test-clean
# run: make test-clean
- name: test-clean
run: make clean
- name: test-verilator
run: make sim-run SIMULATOR=verilator VCD=0

Expand All @@ -59,8 +59,8 @@ jobs:
- uses: actions/checkout@v3
with:
submodules: 'recursive'
#- name: test-clean
# run: make test-clean
- name: test-clean
run: make clean
- name: test-icarus
run: make sim-run SIMULATOR=icarus VCD=0

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8 changes: 4 additions & 4 deletions Makefile
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Expand Up @@ -27,8 +27,8 @@ TESTS+= AddRoundKey

VERSAT_SPEC:=versatSpec.txt

VCD ?= 1
INIT_MEM ?= 1
VCD ?= 0
INIT_MEM ?= 0
USE_EXTMEM ?= 1

ifeq ($(INIT_MEM),1)
Expand Down Expand Up @@ -65,10 +65,10 @@ fpga-run:
make -C ../$(CORE)_V0.70_$(TEST)/ fpga-run BOARD=$(BOARD)

sim-build:
+nix-shell --run 'make setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-build SIMULATOR=$(SIMULATOR) VCD=$(VCD)'
+nix-shell --run 'make setup INIT_MEM=1 USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-build SIMULATOR=$(SIMULATOR) VCD=$(VCD)'

sim-run:
+nix-shell --run 'make setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-run SIMULATOR=$(SIMULATOR) VCD=$(VCD)'
+nix-shell --run 'make setup INIT_MEM=1 USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-run SIMULATOR=$(SIMULATOR) VCD=$(VCD)'

fpga-run-only:
cp ./software/src/Tests/$(TEST).cpp ../$(CORE)_V0.70_$(TEST)/software/src/test.cpp
Expand Down
Empty file added hardware/fpga/quartus/CYCLONEV-GT-DK/.gitkeep
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Empty file.
5 changes: 5 additions & 0 deletions versatSpec.txt
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Expand Up @@ -186,6 +186,10 @@ module TestMergeDelay2(){
mem{5} -> output;
}

/*
// Currently disabled since the generated accelerator uses the same name for different ports
// and the fpga tools complain even when these are not used as top modules

merge TestMergeDelay = TestMergeDelay1 | TestMergeDelay2;

module TestMergeLargeDelay1(){
Expand All @@ -207,6 +211,7 @@ module TestMergeLargeDelay2(){
}

merge TestMergeLargeDelay = TestMergeLargeDelay1 | TestMergeLargeDelay2;
*/

module TestDoubleMerge00(){
Const x00;
Expand Down
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