In this project, we propose to develop a Python framework to (1) manage the files of an embedded hardware/software (HW/SW) codesign project and (2) generate the Verilog code of the hardware components. The flow will use only open-source tools.
An embedded HW/SW project requires that various source files be conveniently organized in a directory tree so that the build scripts can produce the needed artifacts. Typically, Makefiles and different scripting languages are employed, which is often a barrier for new developers. The proposed Python framework will raise developer accessibility by providing a single cockpit for the design process.
Hardware Design Languages such as Verilog and VHDL give a lot of flexibility to users. Still, the design tools reject most of their features and force users to use a small, low-level subset if we want the code to be human-readable and portable to both FPGAs and ASICs. The result is a very tedious and error-prone hardware design process.
Py2HWSW aims to develop a Python generator of portable Verilog code. Py2HW is not a High-Level Synthesis (HLS) language. It is instead a tool to help hardware designers produce readable, lint-clean, and portable Verilog code that can be used seamlessly in any FPGA or ASIC.
Py2HWSW runs on nix-shell and self installs when an example is run. Alternatively you may manuall install the program and all its dependendencies listed in the py2hwsw default.nix file.
The Py2HWSW framework main usage example is IOb-SoC, a System-on-Chip (SoC) template comprising an open-source RISC-V processor, a memory subsystem, and a UART.
Py2HWSW can generate a user guide with LaTeX using the --py2hwsw_docs argument.
To generate a documentation directory with the user guide sources and build it, run:
py2hwsw --py2hwsw_docs
make -C py2hwsw_docs/document/ buildThis project is funded through NGI Zero Core, a fund established by NLnet with financial support from the European Commission's Next Generation Internet program. Learn more at the NLnet project page.
