soc: nordic: nrf54h20: Disable USBHS core cache

Configure USBHS core registers as non-cachable to prevent D-Cache from
inhibiting volatile accesses to the USBHS core registers.

Signed-off-by: Tomasz Moń <[email protected]>

soc/nordic/nrf54h/CMakeLists.txt

@@ -5,6 +5,8 @@ if(CONFIG_ARM)
   zephyr_library_sources(soc.c)
 endif()
 
+zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c)
+
 zephyr_include_directories(.)
 
 # Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes

soc/nordic/nrf54h/Kconfig

@@ -16,6 +16,7 @@ config SOC_NRF54H20_CPUAPP
 	select CPU_HAS_DCACHE
 	select CPU_HAS_ICACHE
 	select CPU_HAS_FPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 
 config SOC_NRF54H20_CPURAD
@@ -27,6 +28,7 @@ config SOC_NRF54H20_CPURAD
 	select CPU_HAS_DCACHE
 	select CPU_HAS_ICACHE
 	select CPU_HAS_FPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 
 config SOC_NRF54H20_CPUPPR

soc/nordic/nrf54h/mpu_regions.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+
+#define USBHS_BASE	DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
+#define USBHS_SIZE	DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
+
+static struct arm_mpu_region mpu_regions[] = {
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usbhs), okay)
+	MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
+			 REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
+#endif
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};