| year | Course | Project name | Description | Key word | Link |
|---|---|---|---|---|---|
| 2022 | SoC Design | SGDE(Sprite Game Display Engine) | Verify the display engine and increase coverage | random pattern generate | repo |
| 2022 | SoC Design | GE(Game Excitation) | Create a game engine using verilog with limited code line | HDL, digital design, random constraint | presentation, report |
| 2022 | VLSI-DSP | FC(Filter Circle) | Demonstrate unsorted and sorted method to find the median with sliding window and minimize the cost or latency | median filter | report |
| 2022 | VLSI-DSP | ES(Engine Show) | Optimize the traditional 13-points discrete cosine transform and minimize the number of multiplier | DCT, folding architecture | presentation, report |
| 2021 | Reliabe System | Analyzing reliability on CNN-based architecture using fault injection | Improve reliability using hardware redundancy which is TMR (Triple Module Redundancy) | reliability | presentation, report |
| 2021 | Undergraduate Project | Reliable Image Convolution Neural Network | Optimized Winograd CNN with cross-minimization adopted on sparse activation improving reliability and testabilty using scan chain | testability, reliability, P&R, tape out | report |
| 2021 | DPAML | Pothole Detection using MaskRCNN Deployed on Jetson Nano | Compress the model with TensorRT | edge computing, model compression | report |
| year | Course | Project name | Description | Key word | Link |
|---|---|---|---|---|---|
| 2022 | ICLab | MH(Morphology Processing Unit) | Image processing unit supported for histogram equalization, erosion and dilation optimized by double flop | Image processing, CDC(Clock Domain Crossing) | no link now |
| 2023 | SoCLab | WLOS(Workload Optimized System) | With workload quick sort, matrix multiplication and FIR run on simple RSIC-V(vex), transmitted data by UART interface and verified on FPGA using PYNQ-Z2 | FPGA, SoC, embedded programming | repo |
| 2023 | VLSI-CAD symposium | Accelerating CNNs for Particle Energy Reconstruction on FPGAs | DeepCalo: An application based on CNN deployed on Alveo U50 with dataflow architecture optimized by quantization-aware training | quantization, FPGA | poster |
| 2024 | research | sequence-length-unrelated transformer architecture with hardware-aware architecture search | ---- | transformer, hls4ml, hls, FPGA, post-training quantization | no link now |