- Torino - Italia
-
05:20
(UTC +01:00) - https://www.polito.it/personale?p=047290
- https://orcid.org/0000-0002-2051-2113
- in/luigi-giuffrida-5470b0175
Highlights
- Pro
Popular repositories Loading
-
-
cv32e40px
cv32e40px PublicForked from esl-epfl/cv32e40px
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog
-
core-v-xif
core-v-xif PublicForked from openhwgroup/core-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
SystemVerilog
-
llvm-project
llvm-project PublicForked from llvm/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
-
x-heep
x-heep PublicForked from esl-epfl/x-heep
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
C
-
len5
len5 PublicForked from vlsi-lab/len5
LEN5 is a coonfigurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
SystemVerilog
If the problem persists, check the GitHub status page or contact support.