Dev/v2024.2 (#24)

Libero SoC 2024.2 Update * Updating the version number of LiberoSoC v2024.1 to LiberoSoC v2024.2 * Legacy Core Designs Removed * Updating with latest FPExpress Jobs
Mi-V-Soft-RISC-V · Nov 14, 2024 · e7985c6 · e7985c6
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diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32IMAF_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32IMA_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32IMA_CFG2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_CFG2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_CFG3_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_DGC2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_AVAL_MIV_RV32_DGC2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md
@@ -1,6 +1,6 @@
 ## Future Avalanche Board FPGA Programming Files
 
-This folder contains FlashPro Express v2024.1 projects for the Future Avalanche Board Mi-V sample designs.
+This folder contains FlashPro Express v2024.2 projects for the Future Avalanche Board Mi-V sample designs.
 
 ## FlashPro Express
 The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
@@ -54,14 +54,3 @@ The peripherals in this design are located at the following addresses.
 | MIV_ESS_APBSLOTE_BASE            | 0x7E00_0000   | 0x7EFF_FFFF    |
 | MIV_ESS_APBSLOTF_BASE            | 0x7F00_0000   | 0x7FFF_FFFF    |
 | SRAM/TCM                         | 0x8000_0000   | 0x8000_7FFF    |
-
-
-#### Legacy core based configurations:
-| Peripheral (Standalone)| Address       |
-| ----------------------:|:-------------:|
-| CoreUARTapb            | 0x7000_1000   |
-| CoreGPIO_IN            | 0x7000_2000   |
-| CoreTimer_0            | 0x7000_3000   |
-| CoreTimer_1            | 0x7000_4000   |
-| CoreGPIO_OUT           | 0x7000_5000   |
-| SRAM                   | 0x8000_0000   |
diff --git a/Libero_Projects/PF_Avalanche_MIV_RV32IMAF_BaseDesign.tcl b/Libero_Projects/PF_Avalanche_MIV_RV32IMAF_BaseDesign.tcl
diff --git a/Libero_Projects/PF_Avalanche_MIV_RV32IMA_BaseDesign.tcl b/Libero_Projects/PF_Avalanche_MIV_RV32IMA_BaseDesign.tcl
diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md
@@ -1,5 +1,5 @@
 ## Future Avalanche Board Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC v2024.1 design projects for the Future Avalanche Board. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.
+This folder contains Tcl scripts that build Libero SoC v2024.2 design projects for the Future Avalanche Board. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.
 
 > MI-V Extended Subsystem Design Guide Configurations:
 > * For **Design Guide Configuration - DGC2: I2C Write & Boot** refer to this [DGC2 README](../docs/design_dgc2/README.md)
@@ -13,21 +13,6 @@ This folder contains Tcl scripts that build Libero SoC v2024.1 design projects f
 | CFG3    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
 
 
-#### PF_Avalanche_MIV_RV32IMA_BaseDesign
-
-| Config  | Description |
-| :------:|:------------|
-| CFG1    | This design uses the MIV_RV32IMA_L1_AHB core with an **AHB** interface for memory and peripherals|
-| CFG2    | This design uses the MIV_RV32IMA_L1_AXI core with an **AXI3** interface for memory and peripherals|
-
-
-#### PF_Avalanche_MIV_RV32IMAF_BaseDesign
-
-| Config  |Description |
-| :------:|:-----------|
-| CFG1    | This design uses the MIV_RV32IMAF_L1_AHB core with an **AHB** interface for memory and peripherals|
-
-
 ## <a name="quick"></a> Instructions
 
 #### Running Libero SoC in GUI mode
@@ -111,13 +96,3 @@ The peripherals in this design are located at the following addresses.
 | MIV_ESS_APBSLOTF_BASE            | 0x7F00_0000   | 0x7FFF_FFFF    |
 | SRAM/TCM                         | 0x8000_0000   | 0x8000_7FFF    |
 
-
-#### Legacy core based configurations:
-| Peripheral (Standalone)| Address       |
-| ----------------------:|:-------------:|
-| CoreUARTapb            | 0x7000_1000   |
-| CoreGPIO_IN            | 0x7000_2000   |
-| CoreTimer_0            | 0x7000_3000   |
-| CoreTimer_1            | 0x7000_4000   |
-| CoreGPIO_OUT           | 0x7000_5000   |
-| SRAM                   | 0x8000_0000   |