Resolve DGC1 and DGC3 MIV_ESS Bootstrap designs issue (#24)

Resolution: - To ensure the correct bootstrap sequence, it is necessary to connect the RESETN signal from MIV_RV32 to the CPU_RESETN signal on MIV_ESS for both DGC design configurations. - uPROM client in DGC3 needs to be flashed with example software provided. Related to [issue #23](#23).
Mi-V-Soft-RISC-V · Aug 18, 2023 · 7fc16d4 · 7fc16d4
1 parent 60114cd
commit 7fc16d4
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Showing 5 changed files with 4 additions and 5 deletions.
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC3_BaseDesign.job
diff --git a/Libero_Projects/import/build_smartdesign/MIV_ESS_build_sd.tcl b/Libero_Projects/import/build_smartdesign/MIV_ESS_build_sd.tcl
@@ -181,6 +181,7 @@ if {$config eq "DGC1"} {
 
 } elseif {$config eq "DGC4"} {
 	# Add scalar net connections
+	sd_connect_pins -sd_name ${sdName} -pin_names "CORERESET_PF_C0_0:FABRIC_RESET_N ${softCpu}_${config}_C0_0:RESETN"
 	sd_connect_pins -sd_name ${sdName} -pin_names "PF_CCC_C0_0:OUT0_FABCLK_0 CoreTimer_C0_0:PCLK" 
 	sd_connect_pins -sd_name ${sdName} -pin_names "PF_CCC_C0_0:OUT0_FABCLK_0 CoreTimer_C1_0:PCLK" 
 	sd_connect_pins -sd_name ${sdName} -pin_names "CORERESET_PF_C0_0:FABRIC_RESET_N CoreTimer_C0_0:PRESETn"
@@ -203,7 +204,6 @@ sd_connect_pins -sd_name ${sdName} -pin_names "PF_CCC_C0_0:OUT0_FABCLK_0 ${sramM
 sd_connect_pins -sd_name ${sdName} -pin_names "CORERESET_PF_C0_0:FABRIC_RESET_N ${sramMemComp}_C0_0:HRESETN"
 
 sd_connect_pins -sd_name ${sdName} -pin_names {"USER_RST" "CORERESET_PF_C0_0:EXT_RST_N"}
-sd_connect_pins -sd_name ${sdName} -pin_names "CORERESET_PF_C0_0:FABRIC_RESET_N ${softCpu}_${config}_C0_0:RESETN"
 sd_connect_pins -sd_name ${sdName} -pin_names "CORERESET_PF_C0_0:FABRIC_RESET_N MIV_ESS_${config}_C0_0:PRESETN"
 sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_C0_0:TGT_TCK_0 ${softCpu}_${config}_C0_0:JTAG_TCK"
 sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_C0_0:TGT_TDI_0 ${softCpu}_${config}_C0_0:JTAG_TDI"
@@ -229,7 +229,6 @@ sd_connect_pins -sd_name ${sdName} -pin_names "GPIO_OUT MIV_ESS_${config}_C0_0:G
 sd_connect_pins -sd_name ${sdName} -pin_names "MIV_ESS_${config}_C0_0:APB_0_mINITIATOR ${softCpu}_${config}_C0_0:APB_INITIATOR"
 sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:AHBL_M_TARGET ${sramMemComp}_C0_0:AHBSlaveInterface"
 
-
 # Re-enable auto promotion of pins of type 'pad'
 auto_promote_pad_pins -promote_all 1
 # Re-arrange SmartDesign layout

diff --git a/Libero_Projects/import/components/dgc/PF_UPROM_C0.tcl b/Libero_Projects/import/components/dgc/PF_UPROM_C0.tcl
@@ -2,6 +2,6 @@
 # Family: PolarFire
 # Part Number: MPF300TS-1FCG484I
 # Create and Configure the core component PF_UPROM_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_UPROM:*} -download_core -component_name {PF_UPROM_C0} -params {\
-"CFGFILE:$scriptDir/import/components/dgc/PF_UPROM_C0_0/UPROM.cfg"   }
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_UPROM:*} -download_core -component_name {PF_UPROM_C0} -params "\
+CFGFILE:$scriptDir/import/components/dgc/PF_UPROM_C0_0/UPROM.cfg "
 # Exporting Component Description of PF_UPROM_C0 to TCL done
diff --git a/Libero_Projects/import/components/dgc/PF_UPROM_C0_0/UPROM.cfg b/Libero_Projects/import/components/dgc/PF_UPROM_C0_0/UPROM.cfg
@@ -4,5 +4,5 @@ set_data_storage_client \
    -use_for_simulation {0}  \
    -content_type {MEMORY_FILE}  \
    -memory_file_format {Intel-Hex}  \
-   -memory_file {miv-rv32i-systick-blinky.hex}  \
+   -memory_file {hex/miv-rv32i-systick-blinky.hex}  \
    -base_address 0