LibSD Update for v2023.1 (#5) (#15)

Libero Scripted Designs Update towards Libero SoC v2023.1
* Notice added to Libero_Project and FlashPro_Express_Projects regarding the work around for the MTVEC issue for FreeRTOS and the Fast Interrupt issue in the latest release of the MIV_RV32.  Please read the readme files in each of those folders to see if you are effected.

* MIV_RV32 in the designs has been updated from: v3.0.100 to v3.1.100. Some of the new features include: RISC-V F Extension and I-Cache.
* Refactored TCL script library, updated for modularity, parameterization and input handling
  * New dynamic paths added, should allow for better performance on non-Windows based OS systems.
  * Design components are now downloaded dynamically for each design configuration
  * Removed glitches which may have been seen when adapting the designs for VHDL
  * Project folders for ES designs have been uniquified for traceability
  * Project folders for MIV_RV32, MIV_RV32IMAF and MIV_RV32IMA have been uniquified for clarity and traceability
* Improved TCL output messaging with regards to the design building and design flow progression
* An example software program has been added to LSRAM-based configurations. After programming the bitstream, software boots out of the box from the LSRAM.
* The clocking circuitry in all of the designs has been improved. A new dedicated clock reference 50MHz clock for the CCC has been added by replacing the OSC macro. Timing has been improved across the designs.
* FlashPro_Express_Projects have been updated to reflect the latest design changes

FlashPro_Express_Projects/README.md

@@ -1,6 +1,22 @@
 # RTG4 Development Kit FPGA Programming Files
 
-This folder contains FlashPro Express v2022.2 projects for the RTG4 Development Kit Mi-V sample designs.
+This folder contains FlashPro Express v2023.1 projects for the RTG4 Development Kit Mi-V sample designs.
+
+## Notice
+1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+
+2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+
+.macro STORE_CONTEXT
+addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
+SREG x1, 0 * REGBYTES(sp)
+SREG x1, 0 * REGBYTES(sp) // re-write the return address to workaround
+SREG x2, 1 * REGBYTES(sp)
+SREG x3, 2 * REGBYTES(sp)
+
+Please see the latest MIV_RV32 HAL available [here](https://github.com/Mi-V-Soft-RISC-V/platform/tree/main/miv_rv32_hal).
+
+A new version of the MIV_RV32 will be released to fix both the issues mentioned above.
 
 ## FlashPro Express
 The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.

Libero_Projects/README.md

@@ -1,15 +1,32 @@
 # RTG4 Development Kit Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC v2022.2 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
+This folder contains Tcl scripts that build Libero SoC v2023.1 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
 
 > This design only supports the production silicon (PS) die
 
+## Notice
+1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+
+2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+
+.macro STORE_CONTEXT
+addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
+SREG x1, 0 * REGBYTES(sp)
+SREG x1, 0 * REGBYTES(sp) // re-write the return address to workaround
+SREG x2, 1 * REGBYTES(sp)
+SREG x3, 2 * REGBYTES(sp)
+
+Please see the latest MIV_RV32 HAL available [here](https://github.com/Mi-V-Soft-RISC-V/platform/tree/main/miv_rv32_hal).
+
+A new version of the MIV_RV32 will be released to fix both the issues mentioned above.
+
+
 #### RTG4_Dev_Kit_MIV_RV32_BaseDesign
 
 | Config  | Description|
 | :------:|:----------------------------------------|
-| CFG1    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
-| CFG2    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled* </li></ul>|
-| CFG3    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
+| CFG1    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHBL Initiator (mirrored), APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
+| CFG2    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled* </li></ul>|
+| CFG3    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
 
 
 #### RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign