Merge pull request #2 from Mi-V-Soft-RISC-V/develop

Merge to master Libero v2021.2 designs

FlashPro_Express_Projects/README.md

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+# RTG4 Development Kit FPGA Programming Files
+
+This folder contains FlashPro Express v2021.2 projects for the RTG4 Development Kit Mi-V sample designs.
+
+## FlashPro Express
+The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
+
+## Programming the Device using FlashPro Express
+ Before running these steps, connect the FPGA board to the computer using FlashPro5 or Embedded FlashPro and power up the board.
+
+    1. Open FlashPro Express
+    2. Select Project -> New Job Project from FlashPro Express Job
+    3. Browse to the programming Job file (.job) using "Browse ...". The Job files are located
+       in the FlashPro_Express_Project/Programming_Files directory
+    4. Select the Job file, then select "Open"
+    5. Select the FlashPro_Express_Project folder (or any folder of your choice) as the project
+       location, then select "OK"
+    6. The FlashPro Express Job Project is created
+    7. Select the "RUN" button; the status bar will change from IDLE to the percentage complete
+    8. Once complete the status bar will display "1 PROGRAMMER(S) PASSED"
+
+## Design Features
+The Libero designs include the following features:
+* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A RISC-V debug block allowing on-target debug using SoftConsole
+* The operating frequency of the design is 50MHz
+* Target memory is SRAM (32kB)
+* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
+
+The peripherals in this design are located at the following addresses.
+
+| Peripheral    | Address   |
+| ------------- |:-------------:|
+| CoreUARTapb   | 0x7000_1000   |
+| CoreGPIO_IN   | 0x7000_2000   |
+| CoreTimer_0   | 0x7000_3000   |
+| CoreTimer_1   | 0x7000_4000   |
+| CoreGPIO_OUT  | 0x7000_5000   |
+| SRAM| 0x8000_0000|

Libero_Projects/README.md

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+# RTG4 Development Kit Mi-V Sample FPGA Designs
+This folder contains Tcl scripts that build Libero SoC v2021.2 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
+
+#### RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign
+
+| Config  | Description |
+| :------:|:------------|
+| CFG1    |This design uses the MIV_RV32IMA_L1_AHB core with an **AHB** interface for memory and peripherals|
+| CFG2    |This design uses the MIV_RV32IMA_L1_AXI core with an **AXI3** interface for memory and peripherals|
+
+
+#### RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign
+
+| Config  |Description |
+| :------:|:-----------|
+| CFG1    |  This design uses the MIV_RV32IMAF_L1_AHB core with an **AHB** interface for memory and peripherals|
+
+
+#### RTG4_Dev_Kit_MIV_RV32_BaseDesign
+
+
+| Config  | Description|
+| :------:|:----------------------------------------|
+| CFG1    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
+| CFG2    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled* </li></ul>|
+| CFG3    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
+
+
+## <a name="quick"></a> Instructions
+
+#### Running Libero SoC in GUI mode
+    1. Open Libero SoC
+    2. Execute the script, Project -> Execute Script
+    3. Select the directory that the script is located in using the "..."
+    4. Select the script and select "Open"
+    5. In the arguments text box, enter the type of configuration you want e.g. "CFG1"
+    6. Select the "Run" button to execute the script
+    7. Once complete, a script report will be generated.
+
+Libero executes the script and opens the Mi-V sample project. The script adds Timing constraints to the project for Synthesis, Place and Route, and Timing Verification. Additionally, IO Constraints are added to the project for Place and Route. The project can now be taken through the remainder of the Libero SoC design flow.
+
+#### Running Libero SoC in GUI mode, with Script Arguments
+    1. Open Libero SoC
+    2. Execute the selected script, Project -> Execute Script
+    3. Select the directory that the script is located in, using the "..."
+    4. Select the script and select "Open"
+    5. In the arguments text box, enter "CFG1 SYNTHESIZE"
+    6. Select the "Run" button to execute the script
+    7. Once complete, a script report will be generated.
+
+In this example, the arguments "CFG1 SYNTHESIZE" are entered to take the project through to Synthesis.
+
+Libero executes the script and opens the Mi-V sample project. The script adds Timing constraints to the project for Synthesis, Place and Route, and Timing Verification. Additionally, IO Constraints are added to the project for Place and Route. The project can now be taken through the remainder of the Libero SoC design flow.
+
+## <a name="Script arguments"></a> Script Arguments
+In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE" were entered. The complete set of script arguments are documented here.
+
+#### First argument:
+| Argument                  |  Description   |
+| ------------------------- |:---------------|
+| CFG1..CFGn                | Generate a sample design for the selected configuration  |
+
+
+#### Second argument:
+| Argument                  |  Description   |
+| ------------------------- |:---------------|
+| SYNTHESIZE                | Run synthesis on the design  |
+| PLACE_AND_ROUTE           | Run place and route on the design  |
+| GENERATE_BITSTREAM        | Generate the bitstream for the design|
+| EXPORT_PROGRAMMING_FILE   | Export the programming file (.job) |
+
+## Design Features
+The Libero designs include the following features:
+* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A RISC-V debug block allowing on-target debug using SoftConsole
+* The operating frequency of the design is 40MHz **(The hw_platform.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
+* Target memory is SRAM (32kB)
+* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
+
+The peripherals in this design are located at the following addresses.
+
+| Peripheral    | Address   |
+| ------------- |:-------------:|
+| CoreUARTapb   | 0x7000_1000   |
+| CoreGPIO_IN   | 0x7000_2000   |
+| CoreTimer_0   | 0x7000_3000   |
+| CoreTimer_1   | 0x7000_4000   |
+| CoreGPIO_OUT  | 0x7000_5000   |
+| SRAM| 0x8000_0000|
+

Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl

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+set project_folder_name_CFG1 MIV_CFG1_BD
+set project_dir_CFG1 "./$project_folder_name_CFG1"
+set Libero_project_name_CFG1 RTG4_Dev_Kit_MIV_RV32IMAF_CFG1_BaseDesign
+
+set config [string toupper [lindex $argv 0]]
+set design_flow_stage [string toupper [lindex $argv 1]]
+
+
+proc create_new_project_label { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Creating a new project for the 'RTG4_Dev_Kit' board."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc project_exists { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Error: A project exists for the 'RTG4_Dev_Kit' with this configuration."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_first_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 1st Argument has been entered."
+	puts "Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' " 
+	puts "Default 'CFG1' design has been selected."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_first_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 1st Argument has been entered."
+    puts "Make sure you enter a valid first argument -'CFG1..CFGn'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_second_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 2nd Argument has been entered."
+	puts "Enter the 2nd Argument after the 1st to be taken further in the Design Flow." 
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_second_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 2nd Argument has been entered."
+    puts "Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc  base_design_built { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "BaseDesign built."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc download_cores_all_cfgs  { }\
+{
+	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
+	#download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+}
+
+proc pre_configure_place_and_route { }\
+{
+    # Configuring Place_and_Route tool for a timing pass.
+    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true}
+}
+
+proc run_verify_timing { }\
+{
+	run_tool -name {VERIFYTIMING}	
+}
+
+if {"$config" == "CFG1"} then {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$config" != ""} then {
+		invalid_first_argument
+} else {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		no_first_argument_entered
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} 
+
+	pre_configure_place_and_route
+
+if {"$design_flow_stage" == "SYNTHESIZE"} then {
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Synthesis..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+    run_tool -name {SYNTHESIZE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Synthesis Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Place and Route..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	run_verify_timing
+	save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Place and Route Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Generating Bitstream..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	run_verify_timing
+    run_tool -name {GENERATEPROGRAMMINGDATA}
+    run_tool -name {GENERATEPROGRAMMINGFILE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Bitstream Generated."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Exporting Programming Files..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	run_verify_timing
+	run_tool -name {GENERATEPROGRAMMINGFILE}
+
+		export_prog_job \
+			-job_file_name {RTG4_Dev_Kit_MIV_RV32IMAF_CFG1_BaseDesign} \
+			-export_dir {./MIV_CFG1_BD/designer/BaseDesign/export} \
+			-force_rtg4_otp 0 \
+			-design_bitstream_format {PPD} 
+		save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Programming Files Exported."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+} elseif {"$design_flow_stage" != ""} then {
+	invalid_second_argument
+} else {
+	no_second_argument_entered
+}