Merge branch 'main' of https://github.com/Mi-V-Soft-RISC-V/RTG4-Devel…

…opment-Kit into main

FlashPro_Express_Projects/README.md

@@ -1,11 +1,11 @@
 # RTG4 Development Kit FPGA Programming Files
 
-This folder contains FlashPro Express v2023.1 projects for the RTG4 Development Kit Mi-V sample designs.
+This folder contains FlashPro Express v2024.1 projects for the RTG4 Development Kit Mi-V sample designs.
 
 ## Notice
-1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples. 
 
-2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.
 
 .macro STORE_CONTEXT
 addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
@@ -37,7 +37,7 @@ The programming files contained under this folder were exported from the designs
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V processor operating at 40 MHz **(The hw_platform.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
+* A soft RISC-V processor operating at 40 MHz **(The fpga_design_config.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * An Extended Subsystem with integrated peripherals
 * Target SRAM/TCM memory (32kB)

Libero_Projects/README.md

@@ -1,12 +1,12 @@
 # RTG4 Development Kit Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC v2023.1 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
+This folder contains Tcl scripts that build Libero SoC v2024.1 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
 
 > This design only supports the production silicon (PS) die
 
 ## Notice
-1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples. 
 
-2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.
 
 .macro STORE_CONTEXT
 addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
@@ -96,7 +96,7 @@ In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE PS" were entered
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V processor operating at 40 MHz **(The hw_platform.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
+* A soft RISC-V processor operating at 40 MHz **(The fpga_design_config.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * An Extended Subsystem with integrated peripherals
 * Target SRAM/TCM memory (32kB)

Libero_Projects/import/components/CoreAHBL_C0.tcl

@@ -1,6 +1,6 @@
 # Exporting core CoreAHBL_0 to TCL
 # Exporting Create design command for core CoreAHBL_0
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {CoreAHBL_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {CoreAHBL_C0} -params {\
 "HADDR_SHG_CFG:1"  \
 "M0_AHBSLOT0ENABLE:false"  \
 "M0_AHBSLOT1ENABLE:false"  \

Libero_Projects/import/components/MIV_ESS_C0.tcl

@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300TS-FCG484I
 # Create and Configure the core component MIV_ESS_0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -component_name {MIV_ESS_C0} -download_core -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -component_name {MIV_ESS_C0} -download_core -params {\
 "APBSLOT11ENABLE:false" \
 "APBSLOT12ENABLE:false" \
 "APBSLOT13ENABLE:false" \

Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl

@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG1_C0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG1_C0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:1"  \

Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl

@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG2_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG2_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:0"  \

Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl

@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG3_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG3_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:0"  \

Libero_Projects/import/proc_blocks.tcl

@@ -190,11 +190,15 @@ proc download_required_direct_cores  {hwPlatform softCpu config} {
 	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
-	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -location {www.microchip-ip.com/repositories/DirectCore}
     if {$softCpu eq "MIV_RV32"} {
-        download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
-        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}
-        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}  
+        download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -location {www.microchip-ip.com/repositories/DirectCore} 
+<<<<<<< HEAD
+        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -location {www.microchip-ip.com/repositories/SgCore}
+        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -location {www.microchip-ip.com/repositories/SgCore}   
+=======
+        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -location {www.microchip-ip.com/repositories/SgCore}  
+>>>>>>> main
     }
 	if {$softCpu eq "MIV_RV32IMA_L1_AHB"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} }
 	if {$softCpu eq "MIV_RV32IMA_L1_AXI"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} }
@@ -241,4 +245,4 @@ proc run_verify_timing { } {
 	run_tool -name {VERIFYTIMING}	
 }
 # Procedure blocks end
-#
+#

README.md

@@ -20,11 +20,11 @@ To download or clone the repository:
 
 
 # Libero Projects
-The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2023.1. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository.
+The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2024.1. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository.
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V processor operating at 40 MHz **(The hw_platform.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
+* A soft RISC-V processor operating at 40 MHz **(The fpga_design_config.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)**
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * An Extended Subsystem with integrated peripherals
 * Target SRAM/TCM memory (32kB)
@@ -40,7 +40,7 @@ The FlashPro_Express_Projects folder contains the pre-generated programming file
 # Design Tools
 The following design tools are required.
 
-## Libero SoC v2023.1
+## Libero SoC v2024.1
 [Libero SoC](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#downloads) is Microchip's FPGA design software.
 
 ## FlashPro Express