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Merged CoreTimer example code version 2.5.114.
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@aakash-mchp
aakash-mchp committed Feb 28, 2024
2 parents 2eda4df + 8d5a990 commit 9b62c59
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147 changes: 142 additions & 5 deletions driver-examples/CoreTimer/miv-rv32-coretimer-timer_interrupt/.cproject
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2 changes: 1 addition & 1 deletion driver-examples/CoreTimer/miv-rv32-coretimer-timer_interrupt/.gitignore
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/*debug*/
/.settings/
/*miv-rv32-imc-debug*/
/*miv-rv32-imc-release*/
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17 changes: 13 additions & 4 deletions driver-examples/CoreTimer/miv-rv32-coretimer-timer_interrupt/README.md
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Expand Up @@ -4,12 +4,13 @@
This example program demonstrates the use of the CoreTimer driver used in
continuous interrupt mode. It toggles a LED on and off every second.

There are two different build configurations provided with this project.
There are three different build configurations provided with this project.
which configure this SoftConsole project for RISC-V IMC instruction extension.
The Following configurations are provided with the example.

- miv-rv32-imc-debug
- miv-rv32-imc-release
- legacy-rv32-debug

## How to use this example

Expand All @@ -34,9 +35,17 @@ definition of MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDI

## Target hardware

This example can be targeted at the latest Mi-V Soft Processor MIV_RV32. Choose the build
configurations per the target processor in your design and the supported ISA extensions
that you want to use.
This example can be targeted at the latest Mi-V Soft Processor MIV_RV32. It can also
be used to target the legacy MiV_RV32IMA_L1_AHB designs. Choose the build configurations
per the target processor in your design and the supported ISA extensions that you
want to use.

This application serves as an example for how to enable external interrups using the
PLIC in legacy RV32 designs using the MiV_RV32IMA_L1_AHB design. In this case,
the PLIC interrups are enabled and the External Interrupt handler is invoked.
For the project to work as expected, a build configuration named 'legacy-rv32-debug'
is provided. This build configuration enables the MIV_LEGACY_RV32 macro and includes
the fpga_design_config.h header required for the legacy desing.

All the design specific definitions such as peripheral base addresses, system clock frequency
etc. are included in fpga_design_config.h(hw_config.h).
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2 changes: 1 addition & 1 deletion ...er/miv-rv32-coretimer-timer_interrupt/miv-rv32-coretimer-timer_interrupt hw attach.launch
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Expand Up @@ -56,6 +56,6 @@
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122 changes: 61 additions & 61 deletions ...mer/miv-rv32-coretimer-timer_interrupt/miv-rv32-coretimer-timer_interrupt hw debug.launch
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42 changes: 35 additions & 7 deletions driver-examples/CoreTimer/miv-rv32-coretimer-timer_interrupt/src/application/main.c
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Expand Up @@ -28,7 +28,7 @@ uint8_t g_message[] =
* This value is calculated to result in the timer timing out after after 1 second with a system
* clock of 83MHz and the timer prescaler set to divide by 1024.
*/
#define TIMER_LOAD_VALUE 81050
#define TIMER_LOAD_VALUE 500000

/*--------------------------------------------------------------------------------------------------
* GPIO instance
Expand All @@ -41,10 +41,22 @@ gpio_instance_t g_gpio;
timer_instance_t g_core_timer_0;

/*--------------------------------------------------------------------------------------------------
* Interrupt handler for the MIV_RV32 MSYS_EI interrupt connected to CoreTimer 0
* In the MIV_RV32 processor design, The CoreTimer interrupt is connected to the
* MSYS_EI0 pin. There is no PLIC inside the MIV_RV32 processor. The CoreTimer
* interrupt is treated as local interrupt and the interrupt handler function,
* MSYS_EI0_IRQHandler(void), is invoked directly by the HAL.
*
* In the designs with legacy processor such as MiV_RV32IMA_L1_AHB, The CoreTimer
* interrupt is connected to External Interrupt pin 30 of the RV32IMA processor.
* It then gets rounted to the PLIC in-build in the RV32IMA processor.
* The interrupt handler function External_30_IRQHandler(void) is called by the
* PLIC/External interrupt handler in the HAL.
*/
uint8_t
MSYS_EI0_IRQHandler(void)
#ifndef MIV_LEGACY_RV32
uint8_t MSYS_EI0_IRQHandler(void)
#else
uint8_t External_30_IRQHandler(void)
#endif
{
/* WARNING!
* In case of modifying this example project, be aware of the time it takes for the interrupt
Expand All @@ -59,6 +71,7 @@ MSYS_EI0_IRQHandler(void)
* Invert the state of GPIO pins 0 - 3 every time the interrupt is triggered
*/
gpio_pins_state = gpio_pins_state ^ (GPIO_0_MASK | GPIO_1_MASK | GPIO_2_MASK | GPIO_3_MASK);
UART_polled_tx_string(&g_core_uart_0, "\rTMR\n");

GPIO_set_outputs(&g_gpio, gpio_pins_state);

Expand All @@ -67,17 +80,32 @@ MSYS_EI0_IRQHandler(void)
return (EXT_IRQ_KEEP_ENABLED);
}

int
main(void)
int main(void)
{
/* Initialise the UART and print the greeting message*/
UART_init(&g_core_uart_0, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, DATA_8_BITS | NO_PARITY);

UART_polled_tx_string(&g_core_uart_0, g_message);

#ifndef MIV_LEGACY_RV32
/* Enable local interrupt for the MSYS_EI interrupt pin */
MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);

/*
* The legacy RV32IMA design uses External Interrupts and an in-built PLIC for interrupt handling.
* To use this project with the Legacy RV32IMA designs, the following initializations
* need to be used.
*
* First we need to enable the PLIC and then we can enable specific interrups which can be enabled
* as per the requirement of the applicaiton. In this case, the CoreTimer0 is connected to external
* interrupt 30, and has been enabled below.
*/
#else
MRV_PLIC_init();
MRV_PLIC_enable_irq(External_30_IRQn);
#endif


/* Initialise the GPIO */
GPIO_init(&g_gpio, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);

Expand All @@ -88,7 +116,7 @@ main(void)
TMR_init(&g_core_timer_0,
CORETIMER0_BASE_ADDR,
TMR_CONTINUOUS_MODE,
PRESCALER_DIV_1024,
PRESCALER_DIV_256,
TIMER_LOAD_VALUE);

/* Enable interrupts in general.*/
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