Merged miv-rv32-hal source code version 2.1.102.

Mi-V-Soft-RISC-V · May 15, 2023 · b33f91f · b33f91f
2 parents 1ca2e1e + fd1daa9
commit b33f91f
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Showing 70 changed files with 14,640 additions and 4,990 deletions.
diff --git a/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/.cproject b/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/.cproject
diff --git a/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/.gitignore b/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/.gitignore
@@ -1,4 +1,4 @@
 /*Debug*/
 /*Release*/
 /.settings*/
-
+/README.html
diff --git a/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/README.md b/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/README.md
@@ -33,7 +33,7 @@ that you are using are compatible with each other.
  - miv32imc-Debug
  - miv32imc-Release
 
-## fpga_design_config (formerly known as hw_config.h)
+## fpga_design_config (formerly known as hw_platform.h)
 The SoftConsole project targeted for Mi-V processors now use an improved
 directory structure. Detailed description of the folder structure is available
 at https://github.com/Mi-V-Soft-RISC-V/miv-rv32-documentation.
@@ -55,7 +55,7 @@ you want a CoreUARTapb mapped to STDIO, etc.
 
 ```
  **NOTE:**
- In the legacy folder structures, the hw_config.h  at the root of the project
+ In the legacy folder structures, the hw_platform.h  at the root of the project
  folder was used to store these configurations. This file is now **DEPRECATED**.
 
  The MIV_RV32 HAL still supports the legacy folder structure with hw_platform.h.

diff --git a/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/src/application/main.c b/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky/src/application/main.c
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
+ * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -10,8 +10,8 @@
 #include <stdio.h>
 #include "hal/hal.h"
 #include "miv_rv32_hal/miv_rv32_hal.h"
-#include "drivers/fabric_ip/CoreGPIO/core_gpio.h"
-#include "drivers/fabric_ip/CoreUARTapb/core_uart_apb.h"
+#include "drivers/fpga_ip/CoreGPIO/core_gpio.h"
+#include "drivers/fpga_ip/CoreUARTapb/core_uart_apb.h"
 
 const char * g_hello_msg =
 "\r\n******************************************************************************\r\n\n\
@@ -49,8 +49,7 @@ void SysTick_Handler(void)
     static volatile uint32_t val = 0u;
     val ^= 0xFu;
     GPIO_set_outputs(&g_gpio_out, val);
-    UART_polled_tx_string(&g_uart,
-                        (const uint8_t *)"\r\nInternal System Timer Interrupt");
+    printf("\r\nInternal System Timer Interrupt");
 }
 
 /*-------------------------------------------------------------------------//**
@@ -67,7 +66,7 @@ int main(void)
               BAUD_VALUE_115200,
               (DATA_8_BITS | NO_PARITY));
 
-    UART_polled_tx_string(&g_uart, (const uint8_t *)g_hello_msg);
+    printf(g_hello_msg);
 
     /* Initializing GPIOs */
     GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
@@ -77,7 +76,15 @@ int main(void)
      * This configuration can not be changed by the firmware since it is fixed in
      * the CoreGPIO IP instance. In your Libero design if you do not make
      * the GPIO configurations 'fixed', then you will need to configure them
-     * using GPIO_config() function*/
+     * using GPIO_config() function
+	 * 
+	 * However, the Renode currently doesn't support 'fixed' configurations on 
+	 * CoreGPIO and therefore the GPIO's have to be configured at runtime. 
+	 * Hence, uncomment following lines when targeting Renode:
+     * 
+	 * GPIO_config(&g_gpio_out, 0, GPIO_OUTPUT_MODE);
+     * GPIO_config(&g_gpio_out, 1, GPIO_OUTPUT_MODE);
+	 */
 
     /* set the output value */
     GPIO_set_outputs(&g_gpio_out, 0x0u);

diff --git a/...oards/polarfire-eval-kit/legacy-design/fpga_design/design_description/readme.md b/...oards/polarfire-eval-kit/legacy-design/fpga_design/design_description/readme.md
@@ -1,3 +1,3 @@
-# Desgin desctription
+# Design description
 
- The Libero generated design desctription will be stored here.
+ The Libero generated design description will be stored here.
diff --git a/...ky/src/boards/polarfire-eval-kit/legacy-design/platform_config/driver_config/phy_sw_cfg.h b/...ky/src/boards/polarfire-eval-kit/legacy-design/platform_config/driver_config/phy_sw_cfg.h
@@ -0,0 +1,136 @@
+/***************************************************************************//**
+ * Copyright 2022 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * @file core10gbasekr_phy_sw_cfg.h
+ * @author Microchip FPGA Embedded Systems Solutions
+ * @brief PHY software configuration
+ *
+ */
+
+#ifndef BOARDS_POLARFIRE_EVAL_KIT_PLATFORM_CONFIG_DRIVER_CONFIG_PHY_SW_CFG_H_
+#define BOARDS_POLARFIRE_EVAL_KIT_PLATFORM_CONFIG_DRIVER_CONFIG_PHY_SW_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * Driver versioning macros.
+ */
+#define CORE_VENDOR                     "Microchip"
+#define CORE_LIBRARY                    "Firmware"
+#define CORE_NAME                       "Core10GBaseKR_PHY_Driver"
+#define CORE_VERSION                    "x.x.x"
+
+/***************************************************************************//**
+ * Supported PHY models, used to control compile time inclusion of the
+ * associated PHY sub-drivers.
+ */
+#define CORE10GBASEKR_PHY
+#define PF_XCVR_C10GB
+
+/***************************************************************************//**
+ * Define this macro to enable performance messages in the application.
+ */
+#undef C10GBKR_PERFORMANCE_MESSAGES
+
+/***************************************************************************//**
+ * User config options for overriding driver defaults of Core10GBaseKR_PHY
+ *
+ * These definitions can be overridden by defining the macro and assigning the
+ * desired value.
+ */
+#ifdef CORE10GBASEKR_PHY
+
+/* Main tap limits */
+#undef C10GBKR_LT_MAIN_TAP_MAX_LIMIT
+#undef C10GBKR_LT_MAIN_TAP_MIN_LIMIT
+
+/* Post tap limits */
+#undef C10GBKR_LT_POST_TAP_MAX_LIMIT
+#undef C10GBKR_LT_POST_TAP_MIN_LIMIT
+
+/* Pre tap limits */
+#undef C10GBKR_LT_PRE_TAP_MAX_LIMIT
+#undef C10GBKR_LT_PRE_TAP_MIN_LIMIT
+
+/* Request to be sent to Link Partner
+   0U => Preset
+   1U => Initialize
+ */
+#undef C10GBKR_LT_INITIAL_REQUEST
+
+#undef C10GBKR_LT_INITIALIZE_MAIN_TAP
+#undef C10GBKR_LT_INITIALIZE_POST_TAP
+#undef C10GBKR_LT_INITIALIZE_PRE_TAP
+
+/***************************************************************************//**
+  Override XCVR configurations
+ */
+#undef PF_XCVR_C10GB_REG_VAL_SER_DRV_CTRL
+#undef PF_XCVR_C10GB_REG_VAL_SER_DRV_DATA_CTRL
+#undef PF_XCVR_C10GB_REG_VAL_SER_DRV_CTRL_SEL
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CTRL_0
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CTRL_1
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CMD
+#undef PF_XCVR_C10GB_REG_VAL_SER_RTL_CTRL
+#undef PF_XCVR_C10GB_REG_VAL_DES_CDR_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_CDR_CTRL_3
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFEEM_CTRL_1
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFEEM_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFEEM_CTRL_3
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_EM_CTRL_2
+
+/***************************************************************************//**
+  Override Auto-Negotiation data rate configurations
+ */
+#undef PF_XCVR_C10GB_AN_CFG_DES_RXPLL_DIV
+#undef PF_XCVR_C10GB_AN_CFG_PMA_DES_RSTPD_POWER_DOWN
+#undef PF_XCVR_C10GB_AN_CFG_PMA_SERDES_RTL_CTRL
+#undef PF_XCVR_C10GB_AN_CFG_PMA_DES_RTL_LOCK_CTRL
+#undef PF_XCVR_C10GB_AN_CFG_PMA_DES_RSTPD_POWER_UP
+#undef PF_XCVR_C10GB_AN_CFG_PCS_LRST_R0_RESET_ASSERT
+#undef PF_XCVR_C10GB_AN_CFG_PCS_LRST_R0_RESET_DEASSERT
+
+
+/***************************************************************************//**
+  Override Link Training data rate configurations
+ */
+#undef PF_XCVR_C10GB_LT_CFG_PMA_DES_RSTPD_POWER_DOWN
+#undef PF_XCVR_C10GB_LT_CFG_PMA_DES_RSTPD_POWER_UP
+#undef PF_XCVR_C10GB_LT_CFG_DES_RXPLL_DIV
+#undef PF_XCVR_C10GB_LT_CFG_PMA_SERDES_RTL_CTRL
+#undef PF_XCVR_C10GB_LT_CFG_PMA_DES_DFE_CAL_BYPASS
+#undef PF_XCVR_C10GB_LT_CFG_PCS_LRST_R0_RESET_ASSERT
+#undef PF_XCVR_C10GB_LT_CFG_PCS_LRST_R0_RESET_DEASSERT
+
+#endif /* CORE10GBASEKR_PHY */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* BOARDS_POLARFIRE_EVAL_KIT_PLATFORM_CONFIG_DRIVER_CONFIG_PHY_SW_CFG_H_ */
diff --git a/...blinky/src/boards/polarfire-eval-kit/legacy-design/platform_config/linker/miv-rv32-ram.ld b/...blinky/src/boards/polarfire-eval-kit/legacy-design/platform_config/linker/miv-rv32-ram.ld
@@ -34,7 +34,7 @@ MEMORY
 }
 
 STACK_SIZE          = 2k;               /* needs to be calculated for your application */
-HEAP_SIZE           = 0k;               /* needs to be calculated for your application */
+HEAP_SIZE           = 1k;               /* needs to be calculated for your application */
 
 SECTIONS
 {

diff --git a/...rds/polarfire-eval-kit/miv-rv32-design/fpga_design/design_description/readme.md b/...rds/polarfire-eval-kit/miv-rv32-design/fpga_design/design_description/readme.md
@@ -1,3 +1,3 @@
-# Desgin desctription
+# Design description
 
- The Libero generated design desctription will be stored here.
+ The Libero generated design description will be stored here.
diff --git a/.../src/boards/polarfire-eval-kit/miv-rv32-design/platform_config/driver_config/phy_sw_cfg.h b/.../src/boards/polarfire-eval-kit/miv-rv32-design/platform_config/driver_config/phy_sw_cfg.h
@@ -0,0 +1,136 @@
+/***************************************************************************//**
+ * Copyright 2022 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * @file core10gbasekr_phy_sw_cfg.h
+ * @author Microchip FPGA Embedded Systems Solutions
+ * @brief PHY software configuration
+ *
+ */
+
+#ifndef BOARDS_POLARFIRE_EVAL_KIT_PLATFORM_CONFIG_DRIVER_CONFIG_PHY_SW_CFG_H_
+#define BOARDS_POLARFIRE_EVAL_KIT_PLATFORM_CONFIG_DRIVER_CONFIG_PHY_SW_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * Driver versioning macros.
+ */
+#define CORE_VENDOR                     "Microchip"
+#define CORE_LIBRARY                    "Firmware"
+#define CORE_NAME                       "Core10GBaseKR_PHY_Driver"
+#define CORE_VERSION                    "x.x.x"
+
+/***************************************************************************//**
+ * Supported PHY models, used to control compile time inclusion of the
+ * associated PHY sub-drivers.
+ */
+#define CORE10GBASEKR_PHY
+#define PF_XCVR_C10GB
+
+/***************************************************************************//**
+ * Define this macro to enable performance messages in the application.
+ */
+#undef C10GBKR_PERFORMANCE_MESSAGES
+
+/***************************************************************************//**
+ * User config options for overriding driver defaults of Core10GBaseKR_PHY
+ *
+ * These definitions can be overridden by defining the macro and assigning the
+ * desired value.
+ */
+#ifdef CORE10GBASEKR_PHY
+
+/* Main tap limits */
+#undef C10GBKR_LT_MAIN_TAP_MAX_LIMIT
+#undef C10GBKR_LT_MAIN_TAP_MIN_LIMIT
+
+/* Post tap limits */
+#undef C10GBKR_LT_POST_TAP_MAX_LIMIT
+#undef C10GBKR_LT_POST_TAP_MIN_LIMIT
+
+/* Pre tap limits */
+#undef C10GBKR_LT_PRE_TAP_MAX_LIMIT
+#undef C10GBKR_LT_PRE_TAP_MIN_LIMIT
+
+/* Request to be sent to Link Partner
+   0U => Preset
+   1U => Initialize
+ */
+#undef C10GBKR_LT_INITIAL_REQUEST
+
+#undef C10GBKR_LT_INITIALIZE_MAIN_TAP
+#undef C10GBKR_LT_INITIALIZE_POST_TAP
+#undef C10GBKR_LT_INITIALIZE_PRE_TAP
+
+/***************************************************************************//**
+  Override XCVR configurations
+ */
+#undef PF_XCVR_C10GB_REG_VAL_SER_DRV_CTRL
+#undef PF_XCVR_C10GB_REG_VAL_SER_DRV_DATA_CTRL
+#undef PF_XCVR_C10GB_REG_VAL_SER_DRV_CTRL_SEL
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CTRL_0
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CTRL_1
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CAL_CMD
+#undef PF_XCVR_C10GB_REG_VAL_SER_RTL_CTRL
+#undef PF_XCVR_C10GB_REG_VAL_DES_CDR_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_CDR_CTRL_3
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFEEM_CTRL_1
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFEEM_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFEEM_CTRL_3
+#undef PF_XCVR_C10GB_REG_VAL_DES_DFE_CTRL_2
+#undef PF_XCVR_C10GB_REG_VAL_DES_EM_CTRL_2
+
+/***************************************************************************//**
+  Override Auto-Negotiation data rate configurations
+ */
+#undef PF_XCVR_C10GB_AN_CFG_DES_RXPLL_DIV
+#undef PF_XCVR_C10GB_AN_CFG_PMA_DES_RSTPD_POWER_DOWN
+#undef PF_XCVR_C10GB_AN_CFG_PMA_SERDES_RTL_CTRL
+#undef PF_XCVR_C10GB_AN_CFG_PMA_DES_RTL_LOCK_CTRL
+#undef PF_XCVR_C10GB_AN_CFG_PMA_DES_RSTPD_POWER_UP
+#undef PF_XCVR_C10GB_AN_CFG_PCS_LRST_R0_RESET_ASSERT
+#undef PF_XCVR_C10GB_AN_CFG_PCS_LRST_R0_RESET_DEASSERT
+
+
+/***************************************************************************//**
+  Override Link Training data rate configurations
+ */
+#undef PF_XCVR_C10GB_LT_CFG_PMA_DES_RSTPD_POWER_DOWN
+#undef PF_XCVR_C10GB_LT_CFG_PMA_DES_RSTPD_POWER_UP
+#undef PF_XCVR_C10GB_LT_CFG_DES_RXPLL_DIV
+#undef PF_XCVR_C10GB_LT_CFG_PMA_SERDES_RTL_CTRL
+#undef PF_XCVR_C10GB_LT_CFG_PMA_DES_DFE_CAL_BYPASS
+#undef PF_XCVR_C10GB_LT_CFG_PCS_LRST_R0_RESET_ASSERT
+#undef PF_XCVR_C10GB_LT_CFG_PCS_LRST_R0_RESET_DEASSERT
+
+#endif /* CORE10GBASEKR_PHY */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* BOARDS_POLARFIRE_EVAL_KIT_PLATFORM_CONFIG_DRIVER_CONFIG_PHY_SW_CFG_H_ */
diff --git a/...inky/src/boards/polarfire-eval-kit/miv-rv32-design/platform_config/linker/miv-rv32-ram.ld b/...inky/src/boards/polarfire-eval-kit/miv-rv32-design/platform_config/linker/miv-rv32-ram.ld
@@ -34,7 +34,7 @@ MEMORY
 }
 
 STACK_SIZE          = 2k;               /* needs to be calculated for your application */
-HEAP_SIZE           = 0k;               /* needs to be calculated for your application */
+HEAP_SIZE           = 1k;               /* needs to be calculated for your application */
 
 SECTIONS
 {