This project was created by Michael Geddes and Will Dormer for Queen's University course ELEC 374. The project is a 32-bit RISC-style CPU developed in Verilog for deployment on an Altera Cyclone DE0-CV FPGA Board.
- 32-Bit
- 30 Instructions
- 16.67 MHz Clock Speed
- 2 KiB of Memory
- 16 General Purpose Registers
- Hardware Multiply and Divide
- 1 32-Bit Output Port
- 1 32-Bit Input Port
The CPU has the following instructions:
- ld (Load)
- ldi (Load Immediate)
- st (Store)
- add (Addition)
- sub (Subtraction)
- shr (Shift Right)
- shl (Shift Left)
- ror (Rotate Right)
- rol (Rotate Left)
- and (Bitwise AND)
- or (Bitwise OR)
- addi (Add immediate)
- andi (Bitwise AND with immediate)
- ori (Bitwise OR with immediate)
- mul (Multiply)
- div (Divide)
- neg (Negate)
- not (Bitwise NOT)
- brzr (Branch if zero)
- brnz (Branch if not zero)
- brmi (Branch if negative)
- brpl (Branch if positive)
- jr (Return from procedure)
- jal (Jump and Link)
- in (Read from inport)
- out (Write to outport)
- mfhl (Move from HI register)
- mflo (Move from LO register)
- nop (No operation)
- halt (Stop execution)