Update linux kernel according to plutosdr #2
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Add dt bindings for the Generic IIO fake device driver This driver allows to link a list of device sysfs attributes from either a platform, spi or i2c device to an iio device. This driver should only be used for debug or test purposes. Signed-off-by: Michael Hennerich <[email protected]>
- Fix Oneshot sync may cause JTX links to fail in certain use cases. - Fix adi_adxxxx_dac_digital_logic_enable_set needed for all devices, not just those containing DAC side implementation. Signed-off-by: Michael Hennerich <[email protected]>
This is particular useful in multi-topology setup, where one RX topology uses QPLL without access to it. So RX should be can be delayed, until TX has configured the QPLL. This is more a workaround than a real solution. The proper solution will be available after the all adxcvr core instances have full DRP access. Signed-off-by: Michael Hennerich <[email protected]>
This will allow the SERDES transceiver to better lock their CDR. Signed-off-by: Michael Hennerich <[email protected]>
This will allow a clean probe, in case the device is bound again. Signed-off-by: Michael Hennerich <[email protected]>
This patch adds support for setting the physical->logical lane mapping via devicetree attribute 'adi,logic-lanes-mapping' Signed-off-by: Michael Hennerich <[email protected]>
This will allow a clean probe, in case the device is bound again. Signed-off-by: Michael Hennerich <[email protected]>
New use case with JESD204 Subclass 1 support. Signed-off-by: Michael Hennerich <[email protected]>
Updated the project as a consequence of the HDl project update. The current modification takes into consideration the fact that the data path for the ADC data has changed. The modification is that there is now a single instance of the JESD TPL, the cpack and the ADC data dma. Signed-off-by: Dan Hotoleanu <[email protected]> Signed-off-by: Cristian Pop <[email protected]>
Up to now adt7x10_remove() returns zero unconditionally. Make it return void instead which makes it easier to see in the callers that there is no error to handle. Also the return value of i2c and spi remove callbacks is ignored anyway. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit beee789)
Using regmap lets us use the regmap subsystem for SPI vs. I2C register accesses. It lets us hide access differences in backend code and lets the common code just access registers without knowing their size. We can also use regmap for register caching. Tested-by: Cosmin Tanislav <[email protected]> Reviewed-by: Cosmin Tanislav <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit e1116026e296685a42a1751980a0815a14f91a80)
To simplify the core driver remove function. Signed-off-by: Cosmin Tanislav <[email protected]> Link: https://lore.kernel.org/r/[email protected] [groeck: Adjust to use regmap; only register restore function if needed] Tested-by: Cosmin Tanislav <[email protected]> Reviewed-by: Cosmin Tanislav <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit 07003ac3ed93b274d07f37dc229c916005dfb038)
Describe the only available channel, implement read, write and is_visible callbacks. Also, pass name to core driver for the i2c device so that it can be used to register hwmon device. Signed-off-by: Cosmin Tanislav <[email protected]> Link: https://lore.kernel.org/r/[email protected] [groeck: Adjusted to use regmap] Tested-by: Cosmin Tanislav <[email protected]> Reviewed-by: Cosmin Tanislav <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit a7bad77467fb521a0eb12b08109e8f8b63e109a0)
To simplify the core driver remove function. Signed-off-by: Cosmin Tanislav <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Cosmin Tanislav <[email protected]> Reviewed-by: Cosmin Tanislav <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit 0577cbaf554135c994411ef65925383c4db230ef)
Not used to do anything anymore. Signed-off-by: Cosmin Tanislav <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Cosmin Tanislav <[email protected]> Reviewed-by: Cosmin Tanislav <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit 0812e9c333bc6953c55011cb9a3c07b0a15114aa)
The hwmon subsystem provides means of notifying userspace about events. Use it. Signed-off-by: Cosmin Tanislav <[email protected]> Link: https://lore.kernel.org/r/[email protected] [groeck: Pass hwmon device to interrupt handler] Tested-by: Cosmin Tanislav <[email protected]> Reviewed-by: Cosmin Tanislav <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> (cherry picked from commit fad02286893cf4cfd4ed7db15cdd872553c51193)
New full bandwidth/bypass mode use case. This use cases implements TXMode 18 and RXMode 19. Using M=2, L=8 for both RX and TX. ADCs and DACs are running at 6GHZ, with a lane rate of 24.75G. Signed-off-by: Michael Hennerich <[email protected]>
For GTY4 the DRP encoding for PROGDIV is indentical to the GTH4 Fixes: f1dba78 ("iio: jesd204: axi_adxcvr: Add TX|RX_PROGDIV support") Signed-off-by: Michael Hennerich <[email protected]>
Introduce IIO_VAL_INT_64 to read 64-bit value for channel attribute. Val is used as lower 32 bits. Signed-off-by: Andriy Tryshnivskyy <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jonathan Cameron <[email protected]> Signed-off-by: Michael Hennerich <[email protected]>
AD9082 ADC can sample up to 6GHz. In full bandwidth/bypass mode our sample rate would be > 3^32. We therefore need support for 64-bit. This patch introduces support for optional scaled clocks. Signed-off-by: Michael Hennerich <[email protected]>
In full bandwidth/bypass mode, channels are no longer complex IQ modified. Since DDC/DUC and their NCOs are bypassed. This path adds support for this, but temporarily disables this detection until the tools are updated to handle the revised channel naming for this case. Signed-off-by: Michael Hennerich <[email protected]>
This patch adds support for 64-bit sample rates. Signed-off-by: Michael Hennerich <[email protected]>
This patch adds support for scaled sampl_clk, and 64-bit sample rates. Signed-off-by: Michael Hennerich <[email protected]>
This patch adds a new compatible "adi,axi-ad9081-tx-1.0-real" used whenever samples are not complex IQ modified. Signed-off-by: Michael Hennerich <[email protected]>
…d_raw Make sure extend_name exist before accessing it. Fixes: dced6c9( "iio: adc: cf_axi_adc_core: Support for 64-bit") Signed-off-by: Michael Hennerich <[email protected]>
DT bindings for use of zero-delay mode for AD9545. Signed-off-by: Alexandru Tachici <[email protected]>
Allow the user to setup an N-shot directly from DT by specifying the number of continuous pulses same as setting the clock rate. Signed-off-by: Alexandru Tachici <[email protected]>
For certain phase sources, the DPLL provides a phase slew rate limiting function that places an upper bound on the rate of change of phase passed along to the loop filter. The phase slew rate limiter mitigates the adverse effects of injecting a large phase step into the loop by converting it to a phase ramp with the maximum slope set by the user. Signed-off-by: Alexandru Tachici <[email protected]>
Introduce support for the internal zero-delay mode of ad9545. Internal zero delay mode is a hitless mode (rather than phase buildout operating mode), in which the AD9545 gradually changes the output phase as it realigns to the phase of the new reference. Signed-off-by: Alexandru Tachici <[email protected]>
If a sync_clk is specified and it supports n-shot generation, enable it in order to align the inputs of HMC7044 to the reference phase. Signed-off-by: Alexandru Tachici <[email protected]>
* Update missing JES204B lcpll values, adi_adxxxx_jesd_tx_pll_startup, Missing JES204B lcpll values leads to PLL startup issues * Added call to bitfield JRX_SYSREF_FOR_STARTUP_I NFO, adi_adxxxx_jesd_rx_link_config_set, JRX_SYSREF_FOR_STARTU P_INFO needs to be enabled when part is in Subclass 1 * Added call to bitfield BF_JTX_SYSREF_FOR_STARTU P_INFO, adi_adxxxx_jesd_tx_link_config_set, JTX_SYSREF_FOR_STARTU P_INFO needs to be enabled when part is in Subclass 1 * Modified oneshot sync procedure to include HAL callback that issues a single pulse SYSREF signal, adi_adxxxx_jesd_oneshot_sync, If in single pulse SYSREF mode, procedure requires the pulse to be issued once. * Updated sysref monitor mode phase get function to include write strobe and display phase value correctly, adi_adxxxx_jesd_sysref_monitor_p hase_get, Write strobe is needed for sysref phase to trigger a value update. The phase value needed to be correctly calculated from two bitfield reads. * Fixed incorrect use of "||" to "&&" in adi_adxxxx_jesd_sysref_irq_jitter_ mux_set(), Parameter check was always failing * Modified full bandwidth mode function to support AD9207 and AD9209, with adi_adxxxx_jesd_tx_fbw_sel_set, AD9207 and AD9209 support full bandwidth mode Signed-off-by: Michael Hennerich <[email protected]>
* Use sysref requets callback * Remove adi_ad9081_jesd_sysref_oneshot_sync_done_get() Signed-off-by: Michael Hennerich <[email protected]>
Not available but not used either. Fixes: fatal error: adi_utils.h: No such file or directory Signed-off-by: Dragos Bogdan <[email protected]>
commit 2334de1 upstream. This reverts commit fce3c5c. FIFO is triggered 4 intervals after receiving a byte, it's good when we don't care about the time of reception, but are only interested in the presence of any activity on the line. Unfortunately, this method is not suitable for all tasks, for example, the RS-485 protocol will not work properly, since the state machine must track the request-response time and after the timeout expires, a decision is made that the device on the line is not responding. Signed-off-by: Alexander Shiyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: fce3c5c ("serial: max310x: rework RX interrupt handling") Cc: Thomas Petazzoni <[email protected]> Cc: stable <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
[ Upstream commit b0a85ab ] This reverts commit 51f689c. Because of recent interactions with developers from @umn.edu, all commits from them have been recently re-reviewed to ensure if they were correct or not. Upon review, this commit was found to be incorrect for the reasons below, so it must be reverted. It will be fixed up "correctly" in a later kernel change. This change did not properly unwind from the error condition, so it was not correct. Cc: Kangjie Lu <[email protected]> Acked-by: Jiri Slaby <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
[ Upstream commit 3890e3d ] The macro "spi_register_driver" invokes the function "__spi_register_driver()" which has a return type of int and can fail, returning a negative value in such a case. This is currently ignored and the init() function yields success even if the spi driver failed to register. Fix this by collecting the return value of "__spi_register_driver()" and also unregister the uart driver in case of failure. Cc: Jiri Slaby <[email protected]> Signed-off-by: Atul Gopinathan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
Device property API allows to gather device resources from different sources, such as ACPI. Convert the drivers to unleash the power of device property API. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
The SPI batch read/write operations can be implemented as simple regmap raw read and write, which will also try to do a gather write just as it is done here. Use the regmap raw read and write methods. Signed-off-by: Cosmin Tanislav <[email protected]>
The driver currently does manual register manipulation in multiple places to talk to a specific UART port. In order to talk to a specific UART port over SPI, the bits U1 and U0 of the register address can be set, as explained in the Command byte configuration section of the datasheet. Make this more elegant by creating regmaps for each UART port and setting the read_flag_mask and write_flag_mask accordingly. All communcations regarding global registers are done on UART port 0, so replace the global regmap entirely with the port 0 regmap. Also, remove the 0x1f masks from reg_writeable(), reg_volatile() and reg_precious() methods, since setting the U1 and U0 bits of the register address happens inside the regmap core now. Signed-off-by: Cosmin Tanislav <[email protected]>
SPI can only use 5 address bits, since one bit is reserved for specifying R/W and 2 bits are used to specify the UART port. To access registers that have addresses past 0x1F, an extended register space can be enabled by writing to the GlobalCommand register (address 0x1F). I2C uses 8 address bits. The R/W bit is placed in the slave address, and so is the UART port. Because of this, registers that have addresses higher than 0x1F can be accessed normally. To access the RevID register, on SPI, 0xCE must be written to the 0x1F address to enable the extended register space, after which the RevID register is accessible at address 0x5. 0xCD must be written to the 0x1F address to disable the extended register space. On I2C, the RevID register is accessible at address 0x25. Create an interface config struct, and add a method for toggling the extended register space and a member for the RevId register address. Implement these for SPI. Signed-off-by: Cosmin Tanislav <[email protected]>
I2C implementation on this chip has a few key differences compared to SPI, as described in previous patches. * extended register space access needs no extra logic * slave address is used to select which UART to communicate with To accommodate these differences, add an I2C interface config, set the RevID register address and implement an empty method for setting the GlobalCommand register, since no special handling is needed for the extended register space. To handle the port-specific slave address, create an I2C dummy device for each port, except the base one (UART0), which is expected to be the one specified in firmware, and create a regmap for each I2C device. Add minimum and maximum slave addresses to each devtype for sanity checking. Also, use a separate regmap config with no write_flag_mask, since I2C has a R/W bit in its slave address, and set the max register to the address of the RevID register, since the extended register space needs no extra logic. Finally, add the I2C driver. Signed-off-by: Cosmin Tanislav <[email protected]>
This fixes a corner case where 160MHz or 80MHz reference clock would return error. Include up and equal to 80MHz as supported scaled range. Signed-off-by: Michael Hennerich <[email protected]>
This provides some additional debug information. Signed-off-by: Michael Hennerich <[email protected]>
The "ulpi-phy" compatible string is a part of Xilinx's fix for the USB controller not being able to change the VBUS state commit 340f285 ("usb: phy: Add platform driver support for ULPI phys") wich we are not using anymore. Signed-off-by: Sergiu Cuciurean <[email protected]>
In the PHY datasheet, the typical application for Host or OTG implies a regulator controlled by the PHY's CPEN port. This change removes the Xilinx's fix leftovers and sets VBUS in the correct way. Signed-off-by: Sergiu Cuciurean <[email protected]>
Change the naming from offset to phase. Signed-off-by: Sergiu Cuciurean <[email protected]>
Rename offset to phase. Signed-off-by: Sergiu Cuciurean <[email protected]>
With the changes from commit a9d887d ("pwm: Convert period and duty cycle to u64"), the pwm_capture members were left unmodified. This commit adds the missing changes. Signed-off-by: Sergiu Cuciurean <[email protected]>
This change is a follow-up to commit 4fa760f ("pwm: Convert period and duty cycle to u64"), converting the remaining parameters to u64. Signed-off-by: Sergiu Cuciurean <[email protected]>
Add sysfs interface for PWM phase. Signed-off-by: Sergiu Cuciurean <[email protected]>
Add documentation for the PWM signal phase. Signed-off-by: Sergiu Cuciurean <[email protected]>
This commit appends the phase specification to pwm_apply_args(). Fixes: b2c4ca6 ("drivers: pwm: core: Add offset support"). Signed-off-by: Sergiu Cuciurean <[email protected]>
This commit adds a new member to the pwm_state structure representing the time unit used to express the other arguments. This change increases the granularity of the PWM arguments, giving a wide range of inputs starting from 1 picosecond. Signed-off-by: Sergiu Cuciurean <[email protected]>
Add the documentation for time_unit. Signed-off-by: Sergiu Cuciurean <[email protected]>
Add time unit support for axi-pwmgen. Signed-off-by: Sergiu Cuciurean <[email protected]>
Add documentation for PWM signal time_unit. Signed-off-by: Sergiu Cuciurean <[email protected]>
Add capture() and get_state() ops. Signed-off-by: Sergiu Cuciurean <[email protected]>
This patch adds support for printing the error counters on the second link. In JRX dual link mode the results for the second link will be separated by an additional ':'. Signed-off-by: Michael Hennerich <[email protected]>
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This updates the kernel used by plutosdr.