misc: Fix ISO C forbids casts to union type to match cpp rule

Signed-off-by: Huaqi Fang <[email protected]>
Nuclei-Software · Nov 1, 2024 · 7160c83 · 7160c83
1 parent 6abf034
commit 7160c83
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Showing 4 changed files with 13 additions and 10 deletions.
diff --git a/OS/FreeRTOS/Source/portable/port.c b/OS/FreeRTOS/Source/portable/port.c
@@ -734,7 +734,8 @@ void vPortValidateInterruptPriority(void)
     uint8_t ucCurrentPriority;
 
     /* Obtain the number of the currently executing interrupt. */
-    CSR_MCAUSE_Type mcause = (CSR_MCAUSE_Type)__RV_CSR_READ(CSR_MCAUSE);
+    CSR_MCAUSE_Type mcause;
+    mcause.d = __RV_CSR_READ(CSR_MCAUSE);
     /* Make sure current trap type is interrupt */
     configASSERT(mcause.b.interrupt == 1);
     if (mcause.b.interrupt) {

diff --git a/application/baremetal/cpuinfo/main.c b/application/baremetal/cpuinfo/main.c
@@ -102,7 +102,7 @@ void nuclei_cpuinfo(void)
             }
         }
     }
-    mcfg = (CSR_MCFGINFO_Type)__RV_CSR_READ(CSR_MCFG_INFO);
+    mcfg.d = __RV_CSR_READ(CSR_MCFG_INFO);
     if (mcfg.b.dsp_n1) {
         printf(" Xxldspn1x");
     }
@@ -196,7 +196,7 @@ void nuclei_cpuinfo(void)
 
     /* ILM */
     if (mcfg.b.ilm) {
-        micfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO);
+        micfg.d = __RV_CSR_READ(CSR_MICFG_INFO);
         printf("             ILM:");
         print_size(POWER_FOR_TWO(micfg.b.lm_size - 1) * 256);
         if (micfg.b.lm_xonly) {
@@ -210,7 +210,7 @@ void nuclei_cpuinfo(void)
 
     /* DLM */
     if (mcfg.b.dlm) {
-        mdcfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO);
+        mdcfg.d = __RV_CSR_READ(CSR_MDCFG_INFO);
         printf("             DLM:");
         print_size(POWER_FOR_TWO(mdcfg.b.lm_size - 1) * 256);
         if (mdcfg.b.lm_ecc) {
@@ -221,21 +221,21 @@ void nuclei_cpuinfo(void)
 
     /* ICACHE */
     if (mcfg.b.icache) {
-        micfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO);
+        micfg.d = __RV_CSR_READ(CSR_MICFG_INFO);
         printf("          ICACHE:");
         show_cache_info(POWER_FOR_TWO(micfg.b.set + 3), micfg.b.way + 1, POWER_FOR_TWO(micfg.b.lsize + 2), mcfg.b.ecc);
     }
 
     /* DCACHE */
     if (mcfg.b.dcache) {
-        mdcfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO);
+        mdcfg.d = __RV_CSR_READ(CSR_MDCFG_INFO);
         printf("          DCACHE:");
         show_cache_info(POWER_FOR_TWO(mdcfg.b.set + 3), mdcfg.b.way + 1, POWER_FOR_TWO(mdcfg.b.lsize + 2), mcfg.b.ecc);
     }
 
     /* TLB only present with MMU, when PLIC present MMU will present */
     if (mcfg.b.plic) {
-        mtlbcfg = (CSR_MTLBCFGINFO_Type)__RV_CSR_READ(CSR_MTLBCFG_INFO);
+        mtlbcfg.d = __RV_CSR_READ(CSR_MTLBCFG_INFO);
         printf("             TLB:");
         printf(" MainTLB(set=%lu,way=%lu,entry=%lu,ecc=%lu) ITLB(entry=%lu) DTLB(entry=%lu)\r\n", \
                 POWER_FOR_TWO(mtlbcfg.b.set + 3), mtlbcfg.b.way + 1, LINESZ(mtlbcfg.b.lsize), \

diff --git a/application/baremetal/demo_plic/main.c b/application/baremetal/demo_plic/main.c
@@ -35,7 +35,7 @@ int main(int argc, char **argv)
 
     // Do PLIC present check via CSR MCFGINFO register
     // Just to confirm whether PLIC really present
-    mcfg = (CSR_MCFGINFO_Type)__RV_CSR_READ(CSR_MCFG_INFO);
+    mcfg.d = __RV_CSR_READ(CSR_MCFG_INFO);
     if (mcfg.b.plic == 0) {
         printf("PLIC is not present in this CPU, please check!\n");
         return 0;

diff --git a/application/baremetal/helloworld/main.c b/application/baremetal/helloworld/main.c
@@ -6,9 +6,11 @@
 
 void print_misa(void)
 {
-    CSR_MISA_Type misa_bits = (CSR_MISA_Type) __RV_CSR_READ(CSR_MISA);
-    static char misa_chars[30];
+    CSR_MISA_Type misa_bits;
+    char misa_chars[30];
     uint8_t index = 0;
+
+    misa_bits.d = __RV_CSR_READ(CSR_MISA);
     if (misa_bits.b.mxl == 1) {
         misa_chars[index++] = '3';
         misa_chars[index++] = '2';