[Fix] Support MMIO read/write to non 8-byte aligned address

[sophimao]

Description

When calling fpgaWriteMMIO64 which an offset and size that spans multiple control registers, only the write to the first control register will pass through, and the write that goes into the next control register will get dropped. This change makes sure that if the input offset and size is not aligned to control register base address offset, the upper half of the first control register will be written by fpgaWriteMMIO32 so that the next write will start at control register base address offset.

Collateral (docs, reports, design examples, case IDs):

None

Tests added:

None

Tests run:

Tested with oneAPI SYCL design that reproduces the issue, the run passed with the fix.

[michael-adler]

Looks reasonable to me -- just reading it. Probably could be a bit simpler, but I think it's correct.