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Open-source, RISC-V-based Hardware Security Module

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OpenROAD-flow-scripts design configuration for a fully open-source hardware security module ASIC with IHP's open PDK.

The Design

RISC-V core based on VexRiscv, extended with masked AES as well as a big number multiplication unit. Eight 32KiB SRAM cells to hold firmware, stack, heap etc. Refer to the hardware/software repository for details.

The ASIC

To build the ASIC, set up OpenROAD-flow-scripts, clone this repository as <ORFS-Root>/flow/designs/ihp-sg13g2/hsm and run the build like any other ORFS design.

Caveats

Other than that, the design is ready for tapeout.

Taped-out Build

Find the build taped out on 11/12/2023 in the releases.

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