test1

Cargo.toml

@@ -30,13 +30,15 @@ wasmtime-wast = { path = "crates/wast", version = "=2.0.0" }
 wasmtime-wasi = { path = "crates/wasi", version = "2.0.0" }
 wasmtime-wasi-crypto = { path = "crates/wasi-crypto", version = "2.0.0", optional = true }
 wasmtime-wasi-nn = { path = "crates/wasi-nn", version = "2.0.0", optional = true }
+# dlmalloc = { path = "crates/dlmalloc-rs", version = "0.2.4", features = ['global'] }
 clap = { version = "3.2.0", features = ["color", "suggestions", "derive"] }
 anyhow = "1.0.19"
 target-lexicon = { version = "0.12.0", default-features = false }
 libc = "0.2.60"
 humantime = "2.0.0"
 once_cell = "1.12"
 listenfd = "1.0.0"
+bitflags = "1.2"
 
 [target.'cfg(unix)'.dependencies]
 rustix = { version = "0.35.6", features = ["mm", "param"] }

cranelift/codegen/meta/src/isa/x86.rs

@@ -117,6 +117,14 @@ fn define_settings(shared: &SettingGroup) -> SettingGroup {
         false,
     );
 
+    // Intel-defined CPU features, CPUID level 0x00000007:0 (ecx)
+    let has_pkru = settings.add_bool(
+        "has_pkru",
+        "Has support for PKU.",
+        "PKU: CPUID.00000007H:ECX=0H[bit 3&4]",
+        true,
+    );
+
     let shared_enable_simd = shared.get_bool("enable_simd");
 
     settings.add_predicate("use_ssse3", predicate!(has_ssse3));
@@ -163,6 +171,7 @@ fn define_settings(shared: &SettingGroup) -> SettingGroup {
     settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
     settings.add_predicate("use_bmi1", predicate!(has_bmi1));
     settings.add_predicate("use_lzcnt", predicate!(has_lzcnt));
+    settings.add_predicate("use_pkru", predicate!(has_pkru));
 
     // Some shared boolean values are used in x86 instruction predicates, so we need to group them
     // in the same TargetIsa, for compatibility with code generated by meta-python.
@@ -195,7 +204,11 @@ fn define_settings(shared: &SettingGroup) -> SettingGroup {
         "Broadwell microarchitecture.",
         preset!(haswell && has_fma),
     );
-    let skylake = settings.add_preset("skylake", "Skylake microarchitecture.", preset!(broadwell));
+    let skylake = settings.add_preset(
+        "skylake",
+        "Skylake microarchitecture.",
+        preset!(broadwell && has_pkru),
+    );
     let cannonlake = settings.add_preset(
         "cannonlake",
         "Canon Lake microarchitecture.",

cranelift/codegen/meta/src/shared/instructions.rs

@@ -1930,6 +1930,30 @@ pub(crate) fn define(
         .operands_out(vec![a]),
     );
 
+    ig.push(
+        Inst::new(
+            "rdmemkey",
+            r#"
+        Reading memory key value.
+        "#,
+            &formats.binary,
+        )
+        .operands_in(vec![x, y])
+        .operands_out(vec![a]),
+    );
+
+    ig.push(
+        Inst::new(
+            "wrmemkey",
+            r#"
+        Writing memory key value.
+        "#,
+            &formats.binary,
+        )
+        .operands_in(vec![x, y])
+        .operands_out(vec![a]),
+    );
+
     let I16or32 = &TypeVar::new(
         "I16or32",
         "A scalar or vector integer type with 16- or 32-bit numbers",

cranelift/codegen/src/ir/entities.rs

@@ -211,6 +211,11 @@ impl GlobalValue {
             None
         }
     }
+
+    /// Get a value
+    pub fn get_number(&self) -> u32 {
+        self.0
+    }
 }
 
 /// An opaque reference to a constant.

cranelift/codegen/src/isa/aarch64/lower_inst.rs

@@ -473,6 +473,10 @@ pub(crate) fn lower_insn_to_regs(
                 op
             )));
         }
+
+        Opcode::Rdmemkey | Opcode::Wrmemkey => {
+            panic!("Memory protection key not supported in arm arch!");
+        }
     }
 
     Ok(())

cranelift/codegen/src/isa/s390x/lower.rs

@@ -274,6 +274,10 @@ impl LowerBackend for S390xBackend {
             | Opcode::IfcmpImm => {
                 panic!("ALU+imm and ALU+carry ops should not appear here!");
             }
+
+            Opcode::Rdmemkey | Opcode::Wrmemkey => {
+                panic!("Memory protection key not supported in s390x arch!");
+            }
         }
     }