Simple RISC machine
This project was a collaborative effort with another UBC student
This is a simple RISC computer written in synthesizable verilog that can execute ARM assembly instructions with 16 bit encodings. The instructions are read from an initialized memory and executed in order. The instruction encodings are as follows
MOV with an immediate operand
MOV with a bit shifted operand
ADD with a bit shifted operand
CMP with a bit shifted operand
AND with a bit shifted operand
MVN with a bit shifted operand
LDR with an immediate operand offset to the base adress
STR with an immediate operand offset to the base adress
HALT instruction to stop the execution of instructions and updating of the program counter
