[TODO] Add RV32C support #25
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also fix the illegal instruction handling to raise the exception during execute stage.
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Create this to get some earlier code review. |
| // C0 | ||
| 2'b00: begin | ||
| case (instr_i[15:13]) | ||
| 3'b000: begin |
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One suggestion is to make those constants as macro definitions, which can include both bit [15:13] and bit [1 :0], and put them in common.vh, like the following:
define C_ADDI4SPN (5'b000_00) define C_LW (5'b010_00)
define C_SW (5'b110_00) define C_NOP_ADDI (5'b000_01)
define C_JAL (5'b001_01) define C_J (5'b101_01)
define C_LI (5'b010_01) define C_BEQZ (5'b110_01)
define C_BNEZ (5'b111_01) define C_ADDI16SP_LUI (5'b011_01)
define C_SLLI (5'b000_10) define C_SWSP (5'b110_10)
define C_LWSP (5'b010_10) define C_JR_JALR_MV_ADD (5'b100_10)
`define C_MISC_ALU (5'b100_01)
also fix the illegal instruction handling to raise the exception during execute stage.
The instruction fetch stage need some additional work to get this RV32C fully working.