skip bitstream generation if flat routing is enabled

QuickLogic-Corp · Dec 5, 2024 · d58e6c6 · d58e6c6
1 parent 01f6183
commit d58e6c6
Showing 1 changed file with 11 additions and 0 deletions.
diff --git a/src/Compiler/CompilerOpenFPGA_ql.cpp b/src/Compiler/CompilerOpenFPGA_ql.cpp
@@ -4555,6 +4555,17 @@ bool CompilerOpenFPGA_ql::GenerateBitstream() {
     return true;
   }
 
+
+  // if flat_routing is enabled in VPR, skip bitstream generation
+  // OpenFPGA does not support bitstream generation with flat_routing (fully, yet)
+  // ref: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2256#issuecomment-1498007179
+  if( QLSettingsManager::getStringValue("vpr", "route", "flat_routing") == "checked" ) {
+    Message("##################################################");
+    Message("Skipping Bitstream Generation since flat_routing is enabled in VPR!");
+    Message("##################################################");
+    return true;
+  }
+
 #if UPSTREAM_UNUSED
   if (BitsOpt() == BitstreamOpt::EnableSimulation) {
     std::filesystem::path bit_path =