ql: pp3: installed tests: counter_gclk: enable simulation

Signed-off-by: Paweł Czarnecki <[email protected]>
QuickLogic-Corp · Dec 21, 2021 · 51e4a88 · 51e4a88
1 parent 82382c1
commit 51e4a88
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Showing 2 changed files with 67 additions and 2 deletions.
diff --git a/quicklogic/pp3/tests/features/install_test/counter_gclk/CMakeLists.txt b/quicklogic/pp3/tests/features/install_test/counter_gclk/CMakeLists.txt
@@ -1,10 +1,13 @@
 add_binary_toolchain_test(
     TEST_NAME counter_gclk
+    ARCH      pp3
     DEVICE    ql-eos-s3
     PINMAP    PD64
     PCF       chandalar.pcf
     EXTRA_ARGS "-dump post_verilog"
 
+    ENABLE_SIMULATION
+
     CHECK_CONSTRAINTS
     ASSERT_USAGE  PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
     ASSERT_TIMING fmax>56.0
@@ -18,13 +21,16 @@ add_binary_toolchain_test(
 )
 
 add_binary_toolchain_test(
-    TEST_NAME counter_gclk_wd30
+    TEST_NAME counter_gclk
     SOURCES   "counter_gclk.v"
+    ARCH      pp3
     DEVICE    ql-pp3
     PINMAP    WD30
     PCF       jimbob4.pcf
     EXTRA_ARGS "-dump post_verilog"
 
+    ENABLE_SIMULATION
+
     CHECK_CONSTRAINTS
     ASSERT_USAGE  PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
     ASSERT_TIMING fmax>56.0
@@ -38,13 +44,16 @@ add_binary_toolchain_test(
 )
 
 add_binary_toolchain_test(
-    TEST_NAME counter_gclk_pd64
+    TEST_NAME counter_gclk
     SOURCES   "counter_gclk.v"
+    ARCH      pp3
     DEVICE    ql-pp3
     PINMAP    PD64
     PCF       pd64.pcf
     EXTRA_ARGS "-dump post_verilog"
 
+    ENABLE_SIMULATION
+
     CHECK_CONSTRAINTS
     ASSERT_USAGE  PB-CLOCK=1,PB-GMUX=1,PB-BIDIR=4
     ASSERT_TIMING fmax>40.0

diff --git a/quicklogic/pp3/tests/features/install_test/counter_gclk/counter_gclk_tb.v b/quicklogic/pp3/tests/features/install_test/counter_gclk/counter_gclk_tb.v
@@ -0,0 +1,56 @@
+`timescale 1 ps / 1 ps
+
+`default_nettype none
+
+`define STRINGIFY(x) `"x`"
+
+
+module tb;
+
+	task assert(input a);
+	begin
+		if (a==0) begin
+			$display("******************");
+			$display("* ASSERT FAILURE *");
+			$display("******************");
+			$dumpflush;
+			$finish_and_return(-1);
+		end
+	end
+	endtask
+
+	reg clk;
+	wire [3:0] out;
+	integer i;
+
+
+	`ifdef NO_SPLIT
+		top dut (
+			.clk (clk),
+			.led (out)
+		);
+	`else
+		top dut (
+			.\clk (clk),
+			.\led[0] (out[0]),
+			.\led[1] (out[1]),
+			.\led[2] (out[2]),
+			.\led[3] (out[3])
+		);
+	`endif
+
+	initial begin
+		clk = 1'b0;
+		`ifndef F2B
+			$sdf_annotate(`STRINGIFY(`SDF), dut);
+		`endif
+		$dumpfile(`STRINGIFY(`VCD));
+		$dumpvars;
+		for (i=1; i<64; i=i+1) begin
+			#1000000 clk = 1;
+			#500000 assert(out === (i % 16));
+			#500000 clk = 0;
+		end
+		#25 $finish();
+	end
+endmodule