update wording

docs/conceptual/l2-cache.rst

@@ -13,8 +13,8 @@ on the device. Besides serving requests from the
 for servicing requests from the :ref:`L1 instruction caches <desc-l1i>`, the
 :ref:`scalar L1 data caches <desc-sL1D>` and the
 :doc:`command processor <command-processor>`. The L2 cache is composed of a
-number of distinct channels (16 on :ref:`MI300 <mixxx-note>` and 32 on
-:ref:`MI200 <mixxx-note>` and MI100 series CDNA accelerators at 256B address
+number of distinct channels (16 per XCC on :ref:`MI300 <mixxx-note>`, and 32 on
+:ref:`MI200 <mixxx-note>` and older CDNA accelerators at 256B address
 interleaving) which can largely operate independently. Mapping of incoming
 requests to a specific L2 channel is determined by a hashing mechanism that
 attempts to evenly distribute requests across the L2 channels. Requests that

docs/conceptual/shader-engine.rst

@@ -40,11 +40,11 @@ Scalar L1 data cache (sL1D)
 The Scalar L1 Data cache (sL1D) can cache data accessed from scalar load
 instructions (and scalar store instructions on architectures where they exist)
 from wavefronts in the :doc:`CUs <compute-unit>`. The sL1D is shared between
-multiple CUs (:gcn-crash-course:`36`) -- the exact number of CUs depends on the
-architecture in question (2 CUs in :ref:`MI300 <mixxx-note>`, 2 CUs in
-:ref:`MI200 <mixxx-note>`, and 3 CUs in MI100 and GCN™ GPUs) -- and is
-backed by the :doc:`L2 cache <l2-cache>`. See :doc:`Accelerator and GPU
-hardware specifications <rocm:reference/gpu-arch-specs>` for more information.
+multiple CUs (:gcn-crash-course:`36`). The exact number of CUs depends on the
+architecture in question (2 CUs in the :ref:`MI300 and MI200 series
+<mixxx-note>` and 3 CUs in MI100 and GCN™ GPUs) and is backed by the :doc:`L2
+cache <l2-cache>`. See :doc:`Accelerator and GPU hardware specifications
+<rocm:reference/gpu-arch-specs>` for more information.
 
 In typical usage, the data in the sL1D is comprised of: